Custom IC Design

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Discussion

measuring setup and hold in adel/mastero

Category: Custom IC Design

By hdeshmukhnvidia

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updated over 3 years ago by FormerMember

2 replies • 4190 views
Discussion

When performing Monte Carlo simulation on ADC, APS or XPS MS simulation reports an error

Category: Custom IC Design

By zuiying

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started over 3 years ago

0 replies • 7960 views
Discussion

How to evaluate expressions in ADE Assembler during a Monte Carlo simulation that require results from a single run at nominal conditions?

Category: Custom IC Design

By FormerMember

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updated over 3 years ago by delgsy

2 replies • 4485 views
Discussion

Importing and simulating .cir spice file in Cadence

Category: Custom IC Design

By delgsy

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updated over 3 years ago by delgsy

5 replies • 12428 views
Discussion

Edit Snap Mode is being set to "anyAngle" on startup - Virtuoso XL 6.1.8-64b.500.21

Category: Custom IC Design

By dietSprunk

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updated over 3 years ago by dietSprunk

2 replies • 2238 views
Discussion

cdsterm info sometimes does not show?

Category: Custom IC Design

By kenc184

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updated over 3 years ago by kenc184

8 replies • 11170 views
Discussion

Problem with EM/IR simulation: port name mismatch between SPF file and schematic netlist

Category: Custom IC Design

By ykhuang

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updated over 3 years ago by ykhuang

2 replies • 3971 views
Discussion

Problem in Global/local Optimization

Category: Custom IC Design

By Mostafa A

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updated over 3 years ago by Mostafa A

2 replies • 2045 views
Discussion

is there any way of extracting terminal charge

Category: Custom IC Design

By Yea Chul

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updated over 3 years ago by Yea Chul

2 replies • 7879 views
Discussion

output setup shows a yellow row

Category: Custom IC Design

By sjwprcker

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updated over 3 years ago by sjwprcker

7 replies • 12803 views
Discussion

3-bit flash ADC design

Category: Custom IC Design

By Lohithpras

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updated over 3 years ago by Andrew Beckett

2 replies • 11301 views
Discussion

switch layer when creating a path in 6.1.8?

Category: Custom IC Design

By fireonthesee88

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updated over 3 years ago by Andrew Beckett

1 replies • 8459 views
Discussion

VerilogA End of File

Category: Custom IC Design

By KhanAmir

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started over 3 years ago

0 replies • 7600 views
Discussion

Empty R reporting in Parasitic Backannotation

Category: Custom IC Design

By delgsy

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updated over 3 years ago by Andrew Beckett

1 replies • 8142 views
Discussion

why schematic and viva trace colors mismatched?

Category: Custom IC Design

By kenc184

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updated over 3 years ago by Andrew Beckett

13 replies • 12305 views

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