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Custom IC Design

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  • Discussion

    the color of instance label in symbol editor

    Category: Custom IC Design

    By zssfred

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    updated over 6 years ago by zssfred

    3 replies • 15433 views
  • Discussion

    Layout versus Schematic design issue

    Category: Custom IC Design

    By NorNand

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    updated over 6 years ago by Andrew Beckett

    4 replies • 15563 views
  • Discussion

    Plotting VerilogA String Variables

    Category: Custom IC Design

    By Tjaart

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    updated over 6 years ago by Andrew Beckett

    4 replies • 16053 views
  • Discussion

    Monte Carlo simulation of noise contributions using SpectreMDL

    Category: Custom IC Design

    By svcher

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    updated over 6 years ago by svcher

    2 replies • 14235 views
  • Discussion

    Print spectre parameters

    Category: Custom IC Design

    By MatthewLove

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    updated over 6 years ago by MatthewLove

    2 replies • 15168 views
  • Discussion

    ERROR [SFE-874]:'Unexpected end of line' while running a .scs file generated using ADE L, cadence Virtuoso v6.1.4 with spectre

    Category: Custom IC Design

    By Chandu D

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    updated over 6 years ago by Chandu D

    18 replies • 21945 views
  • Discussion

    Operating Region of transistors

    Category: Custom IC Design

    By AtaV

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    •

    updated over 6 years ago by Andrew Beckett

    2 replies • 16279 views
  • Discussion

    RE: transient simulation accuracy

    Category: Custom IC Design

    By Kifah

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    updated over 6 years ago by Kifah

    2 replies • 13917 views
  • Discussion

    ADE Assembler - Define IF statement with multiple results arguments (vector)

    Category: Custom IC Design

    By eljuanelo

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    •

    updated over 6 years ago by Andrew Beckett

    3 replies • 1914 views
  • Discussion

    Matlab cadence integration setup

    Category: Custom IC Design

    By AtaV

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    updated over 6 years ago by Andrew Beckett

    3 replies • 18489 views
  • Discussion

    edit schematic annotation will freeze the whole cadence session until I xkill it

    Category: Custom IC Design

    By monglebest

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    updated over 6 years ago by monglebest

    7 replies • 15791 views
  • Discussion

    how to set netSet to connect power of sub-cell to top level cell to pass lvs

    Category: Custom IC Design

    By Nhumai

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    started over 6 years ago

    0 replies • 13309 views
  • Discussion

    LVS issue: short between global net VSS! and gnd

    Category: Custom IC Design

    By isazulkc

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    updated over 6 years ago by Nhumai

    3 replies • 20372 views
  • Discussion

    Annotations are just way too overpowering

    Category: Custom IC Design

    By CADcasualty

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    •

    updated over 6 years ago by CADcasualty

    29 replies • 24983 views
  • Discussion

    PSS Harmonic Balance Analysis, unexpected results

    Category: Custom IC Design

    By MohsenShah

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    •

    updated over 6 years ago by MohsenShah

    4 replies • 14855 views
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