Custom IC Design

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installation issue in Installscape through DVD

Category: Custom IC Design

By conrel

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updated over 8 years ago by Andrew Beckett

1 replies • 13996 views
Discussion

" *Error* asiGetDesignLibName: no applicable method for the class - list" during parametric simulation in ADE

Category: Custom IC Design

By yayla

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updated over 8 years ago by Andrew Beckett

6 replies • 5605 views
Discussion

Convergence difficulties in Verilog A while using equivalent differential equation instead of laplace_nd function

Category: Custom IC Design

By Quilon

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updated over 8 years ago by Andrew Beckett

3 replies • 15591 views
Discussion

Virtuoso Layout XL/GXL -- rasterizing an anyAngle polygon onto a grid

Category: Custom IC Design

By jack.holloway

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updated over 8 years ago by MarkRuiter

2 replies • 3030 views
Discussion

CDS_thru, LVS, new layer

Category: Custom IC Design

By samer1

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updated over 8 years ago by samer1

3 replies • 15006 views
Discussion

varying inline subckt parameter with altergroup in Spectre

Category: Custom IC Design

By sunilm123

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updated over 8 years ago by Andrew Beckett

1 replies • 15112 views
Discussion

$system() command in Verilog-A

Category: Custom IC Design

By farhan89

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updated over 8 years ago by Andrew Beckett

1 replies • 14390 views
Discussion

PDK menu not showing in CIW

Category: Custom IC Design

By wgtkan

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updated over 8 years ago by Andrew Beckett

1 replies • 14977 views
Discussion

ADE simulation setup toolbar missing buttons

Category: Custom IC Design

By wgtkan

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updated over 8 years ago by Andrew Beckett

3 replies • 15206 views
Discussion

How to creat a uniform distribution in source file for Monte-Carlo simulation?

Category: Custom IC Design

By UUinfini

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updated over 8 years ago by lartola

8 replies • 19279 views
Discussion

Plotting Gm vs Vgs for different values of Vbs

Category: Custom IC Design

By wgtkan

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updated over 8 years ago by fatcat1206

4 replies • 24621 views
Discussion

oa2cdb translation

Category: Custom IC Design

By tkhan

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updated over 8 years ago by Andrew Beckett

10 replies • 17931 views
Discussion

RE: ADEXL parametric simulation scalar plot

Category: Custom IC Design

By kenambo

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updated over 8 years ago by kenambo

2 replies • 14354 views
Discussion

Layout Netlist and Topcell Netlist shows correct connections but LVS does not pass!!!

Category: Custom IC Design

By mehdina94rm

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updated over 8 years ago by mehdina94rm

2 replies • 17665 views
Discussion

Should I use the PIN or the NET layer for gnd?

Category: Custom IC Design

By dpalomeq

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updated over 8 years ago by dpalomeq

2 replies • 14000 views

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