Custom IC Design

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Discussion

Assura LVS shows "n_psub_StampErrorMult" error

Category: Custom IC Design

By AdeelAnwar
•
updated over 2 years ago by Andrew Beckett

1 replies • 1360 views
Discussion

VCO phase noise modeling using a transient noise simulation

Category: Custom IC Design

By asrf
•
updated over 2 years ago by Andrew Beckett

32 replies • 21602 views
Discussion

How to remove components from the frequency spectrum

Category: Custom IC Design

By Svilen64
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updated over 2 years ago by Andrew Beckett

2 replies • 7281 views
Discussion

multipole stb probe as actimes

Category: Custom IC Design

By sjwprcker
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started over 2 years ago

0 replies • 6342 views
Discussion

techLibName of a library accidentally changed

Category: Custom IC Design

By delgsy
•
updated over 2 years ago by Andrew Beckett

2 replies • 8519 views
Discussion

Problem when following Quantus Transistor-Level T2: Parasitic Extraction Training

Category: Custom IC Design

By delgsy
•
updated over 2 years ago by Andrew Beckett

3 replies • 6878 views
Discussion

How can I replace a node name with another node name of all schematics in a Library?

Category: Custom IC Design

By ichiro
•
started over 2 years ago

0 replies • 6497 views
Discussion

Adexl - dynamically stop transient run on event trigger

Category: Custom IC Design

By firebolt
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updated over 2 years ago by firebolt

11 replies • 4278 views
Discussion

portorder not being ignored?

Category: Custom IC Design

By kenc184
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updated over 2 years ago by kenc184

8 replies • 10254 views
Discussion

Is it possible to download the slides from online training?

Category: Custom IC Design

By delgsy
•
updated over 2 years ago by Andrew Beckett

1 replies • 6451 views
Discussion

What does the cut pattern "farm" mean?

Category: Custom IC Design

By RVERP
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updated over 2 years ago by RVERP

2 replies • 1055 views
Discussion

RLC parasitic extraction type for post-layout simulation

Category: Custom IC Design

By Senan
•
updated over 2 years ago by Senan

5 replies • 9504 views
Discussion

Digital signal overshoot and undershoot detection in Cadence

Category: Custom IC Design

By Senan
•
updated over 2 years ago by ShawnLogan

3 replies • 8293 views
Discussion

How to acces leaf-instance of subsckt for use as probe?

Category: Custom IC Design

By jehh
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started over 2 years ago

0 replies • 6450 views
Discussion

Spectre parallel jobs reduce near finish

Category: Custom IC Design

By Pirate King
•
updated over 2 years ago by Cadenceuser101

6 replies • 9224 views

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