Custom IC Design

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Discussion

How to get statistical corner by seed and run id in sigma-scaled sampling?

Category: Custom IC Design

By StephanWeber

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updated over 3 years ago by StephanWeber

2 replies • 8929 views
Discussion

A general question about warnings and notices in Virtuoso

Category: Custom IC Design

By MohNaj

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updated over 3 years ago by FormerMember

1 replies • 11528 views
Discussion

How to have a scs file using a design variable or relative path

Category: Custom IC Design

By Pedro P

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updated over 3 years ago by Andrew Beckett

1 replies • 8219 views
Discussion

Input impedence of the differential pair in cadence

Category: Custom IC Design

By muhdnura

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updated over 3 years ago by muhdnura

1 replies • 7815 views
Discussion

Monte-Carlo output for mean+-x*sigma?

Category: Custom IC Design

By StephanWeber

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updated over 3 years ago by Andrew Beckett

6 replies • 5511 views
Discussion

plot problem waveVswave[IM3 vs Pout]

Category: Custom IC Design

By atwinter

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updated over 3 years ago by FormerMember

1 replies • 1574 views
Discussion

Highlight render delay on Virtuoso IC6.1.8

Category: Custom IC Design

By RicardoGV1

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updated over 3 years ago by RicardoGV1

2 replies • 8688 views
Discussion

Vco design virtuoso

Category: Custom IC Design

By Psyliver

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updated over 3 years ago by Psyliver

2 replies • 8952 views
Discussion

Vco design s parameters

Category: Custom IC Design

By Psyliver

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updated over 3 years ago by FormerMember

1 replies • 8507 views
Discussion

measuring setup and hold in adel/mastero

Category: Custom IC Design

By hdeshmukhnvidia

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updated over 3 years ago by FormerMember

2 replies • 4221 views
Discussion

When performing Monte Carlo simulation on ADC, APS or XPS MS simulation reports an error

Category: Custom IC Design

By zuiying

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started over 3 years ago

0 replies • 8004 views
Discussion

How to evaluate expressions in ADE Assembler during a Monte Carlo simulation that require results from a single run at nominal conditions?

Category: Custom IC Design

By FormerMember

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updated over 3 years ago by delgsy

2 replies • 4493 views
Discussion

Importing and simulating .cir spice file in Cadence

Category: Custom IC Design

By delgsy

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updated over 3 years ago by delgsy

5 replies • 12520 views
Discussion

Edit Snap Mode is being set to "anyAngle" on startup - Virtuoso XL 6.1.8-64b.500.21

Category: Custom IC Design

By dietSprunk

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updated over 3 years ago by dietSprunk

2 replies • 2264 views
Discussion

cdsterm info sometimes does not show?

Category: Custom IC Design

By kenc184

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updated over 3 years ago by kenc184

8 replies • 11229 views

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