Custom IC Design

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Calculation of noise multiplication factor (γ) for Ring VCO

Category: Custom IC Design

By Upendra Ch

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updated over 2 years ago by Upendra Ch

5 replies • 8759 views
Discussion

Pin Creation Issue in Virtuoso Layout

Category: Custom IC Design

By POCHAMREDDY

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updated over 2 years ago by RobMan

4 replies • 8366 views
Discussion

Download older version QUANTUS211

Category: Custom IC Design

By zhliang

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updated over 2 years ago by mschw

1 replies • 6535 views
Discussion

Making Spiral Inductor Layout for EM simulations:

Category: Custom IC Design

By Upendra Ch

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updated over 2 years ago by Upendra Ch

4 replies • 8737 views
Discussion

EVM Measurement (envlp analysis)

Category: Custom IC Design

By illaoi

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updated over 2 years ago by illaoi

3 replies • 8245 views
Discussion

Verilog-A: is it possible to nest analog events? e.g. timer() inside cross()?

Category: Custom IC Design

By dontpanic

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updated over 2 years ago by Andrew Beckett

1 replies • 10090 views
Discussion

Veriloga model of load behaves differently when standalone or instantiated with other circuit

Category: Custom IC Design

By unSkilled

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updated over 2 years ago by Andrew Beckett

2 replies • 7124 views
Discussion

Virtuoso ADE SKILL Reference ICADVM20.1: calcVal on a transient expression does not work

Category: Custom IC Design

By NewScreenName

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updated over 2 years ago by Andrew Beckett

1 replies • 7042 views
Discussion

About tsmc65 .proc file:

Category: Custom IC Design

By Upendra Ch

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updated over 2 years ago by Andrew Beckett

1 replies • 8879 views
Discussion

VerilogA simulation error

Category: Custom IC Design

By TUKA

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updated over 2 years ago by TUKA

4 replies • 7658 views
Discussion

issue with assembler running corner simulations

Category: Custom IC Design

By greywanderer

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updated over 2 years ago by Andrew Beckett

1 replies • 6354 views
Discussion

How to derive edge phase noise from Output Noise in sampled Pnoise simulation

Category: Custom IC Design

By mxm14

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updated over 2 years ago by Frank Wiedmann

11 replies • 15942 views
Discussion

Catch glitches on DC signal.

Category: Custom IC Design

By IKIF

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updated over 2 years ago by ShawnLogan

3 replies • 6750 views
Discussion

PLL noise verification problem (Cadence PLL RAK)

Category: Custom IC Design

By KGSpll

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updated over 2 years ago by ShawnLogan

8 replies • 11021 views
Discussion

ADE - MATLAB Integration - get path of maestro cellview / store matlab scripts in different folders

Category: Custom IC Design

By michael10

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updated over 2 years ago by michael10

1 replies • 1158 views

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