Custom IC Design

Latest Posts

Discussion

edit schematic annotation will freeze the whole cadence session until I xkill it

Category: Custom IC Design

By monglebest

$usertype
•
updated over 6 years ago by monglebest

7 replies • 15875 views
Discussion

how to set netSet to connect power of sub-cell to top level cell to pass lvs

Category: Custom IC Design

By Nhumai

$usertype
•
started over 6 years ago

0 replies • 13376 views
Discussion

LVS issue: short between global net VSS! and gnd

Category: Custom IC Design

By isazulkc

$usertype
•
updated over 6 years ago by Nhumai

3 replies • 20520 views
Discussion

Annotations are just way too overpowering

Category: Custom IC Design

By CADcasualty

$usertype
•
updated over 6 years ago by CADcasualty

29 replies • 25237 views
Discussion

PSS Harmonic Balance Analysis, unexpected results

Category: Custom IC Design

By MohsenShah

$usertype
•
updated over 6 years ago by MohsenShah

4 replies • 14947 views
Discussion

ADE Explorer Variables to VerilogA Parameter Arrays

Category: Custom IC Design

By Tjaart

$usertype
•
updated over 6 years ago by Tjaart

2 replies • 15715 views
Discussion

VIVA calculator dnl&inl

Category: Custom IC Design

By Simons

$usertype
•
updated over 6 years ago by Andrew Beckett

3 replies • 3432 views
Discussion

Transient simulation crashes SPECTRE181, APS

Category: Custom IC Design

By Michael H

$usertype
•
updated over 6 years ago by Michael H

2 replies • 15721 views
Discussion

How to access data in info databases in PSF directory?

Category: Custom IC Design

By rawrakesh

$usertype
•
updated over 6 years ago by Andrew Beckett

1 replies • 15155 views
Discussion

Parameter sweep in layout and running extraction

Category: Custom IC Design

By Emiel

$usertype
•
updated over 6 years ago by Andrew Beckett

3 replies • 14975 views
Discussion

Error in running HSPICE NETLIST using cadence virtuoso ADE L

Category: Custom IC Design

By Chandu D

$usertype
•
updated over 6 years ago by Chandu D

2 replies • 18112 views
Discussion

functional mismatch of pre and post layout simulation results

Category: Custom IC Design

By abhi21

$usertype
•
updated over 6 years ago by Andrew Beckett

1 replies • 14767 views
Discussion

[Virtuoso] What is wrong with my RC transient simulation ?

Category: Custom IC Design

By Leey

$usertype
•
updated over 6 years ago by Leey

5 replies • 16742 views
Discussion

CalcVal

Category: Custom IC Design

By Pyroblast

$usertype
•
updated over 6 years ago by Andrew Beckett

1 replies • 13816 views
Discussion

spectre.out file in psf directory

Category: Custom IC Design

By nicola91it

$usertype
•
updated over 6 years ago by Andrew Beckett

3 replies • 17565 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.