Custom IC Design

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Working with tabs in virtuoso schematic editor (opus 6.1.5 - ADE L)

Category: Custom IC Design

By Aldo2

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updated over 13 years ago by Aldo2

7 replies • 4334 views
Discussion

Virtuoso: "save a copy" from read-only cell in 6.1.4 but not in 6.1.5

Category: Custom IC Design

By StefanSL

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updated over 13 years ago by StefanSL

2 replies • 1229 views
Discussion

automatically spacing and aligning instances in Virtuoso schematic editor

Category: Custom IC Design

By MOSFET

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updated over 13 years ago by Andrew Beckett

1 replies • 17225 views
Discussion

Finding the maximum after a parametric analysis with more than one variable

Category: Custom IC Design

By Ueue

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updated over 13 years ago by Andrew Beckett

1 replies • 12918 views
Discussion

How to do a sp simulation using the netlist created by relxpert?

Category: Custom IC Design

By wyliechee

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updated over 13 years ago by Andrew Beckett

3 replies • 13149 views
Discussion

Cadence session crash.

Category: Custom IC Design

By maskdesigner

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updated over 13 years ago by Andrew Beckett

5 replies • 15677 views
Discussion

LVS with Calibre ("wrong floating n-well" error)

Category: Custom IC Design

By Ueue

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updated over 13 years ago by Andrew Beckett

1 replies • 4305 views
Discussion

cross probing with calibre

Category: Custom IC Design

By layout analog

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updated over 13 years ago by Andrew Beckett

1 replies • 13077 views
Discussion

Location of spectre for ADE L

Category: Custom IC Design

By jun1119

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updated over 13 years ago by Andrew Beckett

1 replies • 12950 views
Discussion

VerilogIn pin notation

Category: Custom IC Design

By TjaartOpperman

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updated over 13 years ago by Andrew Beckett

1 replies • 13921 views
Discussion

Measure across a component in cadence ic 6.1.3

Category: Custom IC Design

By jun1119

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updated over 13 years ago by Andrew Beckett

1 replies • 13170 views
Discussion

Assura TIE ivpcell substrateLib not found

Category: Custom IC Design

By Xiongliang

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updated over 13 years ago by Andrew Beckett

1 replies • 13100 views
Discussion

Trendline like Excel

Category: Custom IC Design

By FormerMember

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updated over 13 years ago by Andrew Beckett

1 replies • 4550 views
Discussion

In valid dev or Device Instance in dc analysis of spectre cadence

Category: Custom IC Design

By leonel1408

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updated over 13 years ago by Andrew Beckett

1 replies • 13069 views
Discussion

Is it possible to run DRC in Virtuoso on command line

Category: Custom IC Design

By sanil

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updated over 13 years ago by Andrew Beckett

1 replies • 13531 views

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