Custom IC Design

Latest Posts

Discussion

dcmatch appNote

Category: Custom IC Design

By mate0409

$usertype
•
updated over 13 years ago by FormerMember

5 replies • 14947 views
Discussion

Error: "Vim: Warning: Output is not to a terminal" when trying to open veriloga view

Category: Custom IC Design

By archive

$usertype
•
updated over 13 years ago by skillUser

2 replies • 3706 views
Discussion

command to return the TechLib of the current design window (layout editor window)

Category: Custom IC Design

By jaleco

$usertype
•
updated over 13 years ago by jaleco

3 replies • 13660 views
Discussion

Converting mosaic of syContacts devices from IC5 to IC6 ( cdb2oa )

Category: Custom IC Design

By bnugent

$usertype
•
updated over 13 years ago by bnugent

2 replies • 13231 views
Discussion

Assura41 ELW, VLW resize: CPU load 101%

Category: Custom IC Design

By LayMan

$usertype
•
updated over 13 years ago by LayMan

2 replies • 13429 views
Discussion

Exporting DC operating point

Category: Custom IC Design

By mailavj

$usertype
•
updated over 13 years ago by Andrew Beckett

1 replies • 13497 views
Discussion

Virtuoso ADEGXL: SKILL function falltime(...)

Category: Custom IC Design

By Eberhard2010

$usertype
•
updated over 13 years ago by Andrew Beckett

3 replies • 15377 views
Discussion

Can not get the input noise plotted, IC6.14, MMSIM 10

Category: Custom IC Design

By Kabal

$usertype
•
updated over 13 years ago by Andrew Beckett

2 replies • 13283 views
Discussion

Leakage current calculation using spectre (virtuoso)

Category: Custom IC Design

By Mahaboob

$usertype
•
updated over 13 years ago by Andrew Beckett

1 replies • 14380 views
Discussion

Why spectre generated-netlist always show the wrong subckt name "unmos4_schematic" but not "unmos4" ?

Category: Custom IC Design

By Paulux

$usertype
•
updated over 13 years ago by Andrew Beckett

5 replies • 2610 views
Discussion

Time Delay in VCVS & Delay Block in Spectre (Cadence 5) no influence

Category: Custom IC Design

By tstoll

$usertype
•
updated over 13 years ago by Andrew Beckett

2 replies • 4359 views
Discussion

The resolution of sin wave

Category: Custom IC Design

By Medya

$usertype
•
updated over 13 years ago by Andrew Beckett

10 replies • 19465 views
Discussion

Converttime

Category: Custom IC Design

By Sword1983

$usertype
•
updated over 13 years ago by Andrew Beckett

1 replies • 12723 views
Discussion

How to define double vias in rules file for VCAR

Category: Custom IC Design

By PSRK

$usertype
•
updated over 13 years ago by Andrew Beckett

12 replies • 19371 views
Discussion

Difference between n/p –select and n/p - active layers in CMOS layout techniques.

Category: Custom IC Design

By RAO VINAY

$usertype
•
updated over 13 years ago by Andrew Beckett

1 replies • 2933 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.