Custom IC Design

Latest Posts

Discussion

Cadence PEX Directory Creation - Unable to Create the Directory for Netlist

Category: Custom IC Design

By ranaya
•
updated 23 days ago by ranaya

2 replies • 385 views
Discussion

Cadence Parasitic Extraction - Location / Directory Issue

Category: Custom IC Design

By ranaya
•
updated 23 days ago by Andrew Beckett

1 replies • 282 views
Discussion

Automating Library Reference Change with Additional Parameters in New Library

Category: Custom IC Design

By AN202507174258
•
started 25 days ago

0 replies • 327 views
Discussion

For a new machine, which RHEL?

Category: Custom IC Design

By kenc184
•
updated 26 days ago by kenc184

3 replies • 639 views
Discussion

Parameterization of transistor model BSIM4 parameters

Category: Custom IC Design

By Sourav Chakraborty
•
started 26 days ago

0 replies • 353 views
Discussion

Verilog A: Generate different $random values for each Monte Carlo iteration

Category: Custom IC Design

By MC20250412421
•
updated 28 days ago by MC20250412421

6 replies • 1025 views
Discussion

Convert Cadence Spectre to Cadence Orcad

Category: Custom IC Design

By SC202412036016
•
started 28 days ago

0 replies • 496 views
Discussion

Voltus-Fi-XL : generated path of mergedCurrents.rpt

Category: Custom IC Design

By SY202508201356
•
started 28 days ago

0 replies • 485 views
Discussion

setting environment variables from schematic?

Category: Custom IC Design

By unSkilled
•
started 29 days ago

0 replies • 425 views
Discussion

STB Analysis Breakpoint Selection and Nyquist Plot Support in Cadence

Category: Custom IC Design

By Eleanor Grace
•
updated 1 month ago by JankoK

3 replies • 787 views
Discussion

quantus parasitic extraction vs. SKY130 PDK

Category: Custom IC Design

By GS202507021424
•
started 1 month ago

0 replies • 551 views
Discussion

stb results different when iprobe placed at different location of the loop

Category: Custom IC Design

By a048
•
updated 1 month ago by Frank Wiedmann

3 replies • 808 views
Discussion

giolib045 "archaeology" (origin of giolib045.lib, giolib045.gds files)

Category: Custom IC Design

By GS202507021424
•
started 1 month ago

0 replies • 286 views
Discussion

Schematic editor 2D array signal

Category: Custom IC Design

By kramnik
•
updated 1 month ago by Andrew Beckett

1 replies • 572 views
Discussion

automate creration of calibre view from extraction for multiple extracted corners

Category: Custom IC Design

By micipici
•
updated 1 month ago by Andrew Beckett

1 replies • 635 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.