Custom IC Design

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Discussion

Cadence PEX Directory Creation - Unable to Create the Directory for Netlist

Category: Custom IC Design

By ranaya
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updated 23 days ago by ranaya

2 replies • 385 views
Discussion

Cadence Parasitic Extraction - Location / Directory Issue

Category: Custom IC Design

By ranaya
•
updated 23 days ago by Andrew Beckett

1 replies • 280 views
Discussion

Automating Library Reference Change with Additional Parameters in New Library

Category: Custom IC Design

By AN202507174258
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started 25 days ago

0 replies • 325 views
Discussion

For a new machine, which RHEL?

Category: Custom IC Design

By kenc184
•
updated 25 days ago by kenc184

3 replies • 637 views
Discussion

Parameterization of transistor model BSIM4 parameters

Category: Custom IC Design

By Sourav Chakraborty
•
started 26 days ago

0 replies • 351 views
Discussion

Verilog A: Generate different $random values for each Monte Carlo iteration

Category: Custom IC Design

By MC20250412421
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updated 27 days ago by MC20250412421

6 replies • 1023 views
Discussion

Convert Cadence Spectre to Cadence Orcad

Category: Custom IC Design

By SC202412036016
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started 28 days ago

0 replies • 494 views
Discussion

Voltus-Fi-XL : generated path of mergedCurrents.rpt

Category: Custom IC Design

By SY202508201356
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started 28 days ago

0 replies • 482 views
Discussion

setting environment variables from schematic?

Category: Custom IC Design

By unSkilled
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started 29 days ago

0 replies • 423 views
Discussion

STB Analysis Breakpoint Selection and Nyquist Plot Support in Cadence

Category: Custom IC Design

By Eleanor Grace
•
updated 30 days ago by JankoK

3 replies • 784 views
Discussion

quantus parasitic extraction vs. SKY130 PDK

Category: Custom IC Design

By GS202507021424
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started 1 month ago

0 replies • 549 views
Discussion

stb results different when iprobe placed at different location of the loop

Category: Custom IC Design

By a048
•
updated 1 month ago by Frank Wiedmann

3 replies • 803 views
Discussion

giolib045 "archaeology" (origin of giolib045.lib, giolib045.gds files)

Category: Custom IC Design

By GS202507021424
•
started 1 month ago

0 replies • 286 views
Discussion

Schematic editor 2D array signal

Category: Custom IC Design

By kramnik
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updated 1 month ago by Andrew Beckett

1 replies • 570 views
Discussion

automate creration of calibre view from extraction for multiple extracted corners

Category: Custom IC Design

By micipici
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updated 1 month ago by Andrew Beckett

1 replies • 629 views

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