Custom IC Design

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Virtuoso AMS NOUNIT error with Xcelium - Not caching libraries

Category: Custom IC Design

By AS202502163432

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updated 2 months ago by AS202502163432

8 replies • 1692 views
Discussion

Recovering "actionable" netlist from GDS II

Category: Custom IC Design

By GS202507021424

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updated 2 months ago by GS202507021424

6 replies • 953 views
Discussion

How to reference multiple PWL waveforms from a single file in Spectre (vsource type=pwl)

Category: Custom IC Design

By baltaci

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updated 2 months ago by Andrew Beckett

1 replies • 805 views
Discussion

Copy schematic/symbol views hierarchically

Category: Custom IC Design

By ycau

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updated 2 months ago by Andrew Beckett

2 replies • 554 views
Discussion

Transfer design variable from schematic / layout to av_extracted view

Category: Custom IC Design

By FM202408077836

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updated 2 months ago by Andrew Beckett

2 replies • 1022 views
Discussion

Explanation of stb analysis results YG, YL, ZG, and ZL

Category: Custom IC Design

By Frank Wiedmann

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started 2 months ago

0 replies • 841 views
Discussion

Question on integrated noise in PNOISE (sampled) Noise summary

Category: Custom IC Design

By Yuto Lau

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updated 2 months ago by Yuto Lau

4 replies • 1293 views
Discussion

Automating Layout Cell Updates Using SKILL with Cell List from File

Category: Custom IC Design

By AR202509246930

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updated 2 months ago by Andrew Beckett

1 replies • 1004 views
Discussion

Query regarding Virtuoso EMX tool

Category: Custom IC Design

By VLSI lab IITB

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updated 2 months ago by VLSI lab IITB

4 replies • 1520 views
Discussion

about cadence virtuoso guidance manual problem

Category: Custom IC Design

By JJ202503031042

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updated 2 months ago by JJ202503031042

3 replies • 1337 views
Discussion

Creating Assura DRC rule to check that sep of 2 layers is exactly 2 different values

Category: Custom IC Design

By Miguel V

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started 2 months ago

0 replies • 818 views
Discussion

LVS Warning: “Unattached port label” for PLUS/MINUS on layer ind11_text — can’t locate device

Category: Custom IC Design

By RK202509013321

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updated 2 months ago by RobMan

3 replies • 1091 views
Discussion

Dual Core Oscillator Open Loop

Category: Custom IC Design

By IS20250922772

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started 2 months ago

0 replies • 762 views
Discussion

Assembler: possible to disable automatic evaluation of output expressions?

Category: Custom IC Design

By dontpanic

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updated 2 months ago by Andrew Beckett

1 replies • 952 views
Discussion

Assembler: possible to force inclusion of model file(s) at the very beginning of netlist?

Category: Custom IC Design

By dontpanic

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updated 2 months ago by Andrew Beckett

3 replies • 839 views

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