Custom IC Design

Latest Posts

Discussion

How can you create a global net in a Spectre netlist that does not end in !

Category: Custom IC Design

By FormerMember

$usertype
•
updated over 11 years ago by Andrew Beckett

5 replies • 5962 views
Discussion

From spectremdl to ultrasim : any cadence solution ?

Category: Custom IC Design

By samung

$usertype
•
updated over 11 years ago by samung

7 replies • 16078 views
Discussion

Generating ocean script in Linux terminal.

Category: Custom IC Design

By RFStuff

$usertype
•
updated over 11 years ago by skillUser

3 replies • 15709 views
Discussion

parametric analysis of mosfet length and width

Category: Custom IC Design

By madhanmo

$usertype
•
started over 11 years ago

0 replies • 14803 views
Discussion

Memory instance : ULTRASIM simulator setting

Category: Custom IC Design

By samung

$usertype
•
started over 11 years ago

0 replies • 13970 views
Discussion

ADEXL parametric sweep does not work

Category: Custom IC Design

By sram8t

$usertype
•
updated over 11 years ago by Andrew Beckett

1 replies • 15563 views
Discussion

Extracted parameters do not match with the schematic.

Category: Custom IC Design

By jagadishdn

$usertype
•
updated over 11 years ago by jagadishdn

2 replies • 14954 views
Discussion

How to multiply a waveform with the x axis vector

Category: Custom IC Design

By milind0y

$usertype
•
updated over 11 years ago by milind0y

2 replies • 18247 views
Discussion

Layout Porting between Foundries

Category: Custom IC Design

By KKANDOTH

$usertype
•
updated over 11 years ago by theopaone

5 replies • 17532 views
Discussion

Link pin labels over hierarchy

Category: Custom IC Design

By Narasimhan90

$usertype
•
updated over 11 years ago by Andrew Beckett

3 replies • 14924 views
Discussion

Knowing associated TECH-FILE location

Category: Custom IC Design

By RFStuff

$usertype
•
updated over 11 years ago by Andrew Beckett

3 replies • 19505 views
Discussion

Entering infoname and info (captab) analysis in ADE

Category: Custom IC Design

By RFStuff

$usertype
•
updated over 11 years ago by Andrew Beckett

3 replies • 17767 views
Discussion

Processing cadence result data from psf folder

Category: Custom IC Design

By RFStuff

$usertype
•
updated over 11 years ago by Andrew Beckett

7 replies • 22454 views
Discussion

NC-Verilog netlister setttings to output single netlist (not hierarchy-ihnl/ based)

Category: Custom IC Design

By jagarcia85

$usertype
•
updated over 11 years ago by Andrew Beckett

3 replies • 16065 views
Discussion

Zoom-in and Zoom-out graphics issues in Virtuso Layout Editor ( IC5141-sub-version 5.10.41.500.6.151)

Category: Custom IC Design

By RFStuff

$usertype
•
updated over 11 years ago by Andrew Beckett

1 replies • 16138 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.