Custom IC Design

Latest Posts

Discussion

Monte Carlo Ocean XL: can not delete history in a loop

Category: Custom IC Design

By Martyniuk

$usertype
•
updated over 6 years ago by Martyniuk

3 replies • 17034 views
Discussion

How to add an accurate triggered clock in a testbench

Category: Custom IC Design

By RFStuff

$usertype
•
updated over 6 years ago by Andrew Beckett

3 replies • 16938 views
Discussion

spectre terminated prematurely due to fatal error.

Category: Custom IC Design

By hTmTech

$usertype
•
updated over 6 years ago by Andrew Beckett

7 replies • 28072 views
Discussion

Maestro: Use Simulation sweep variable in output equation

Category: Custom IC Design

By HoWei

$usertype
•
updated over 6 years ago by Andrew Beckett

8 replies • 22056 views
Discussion

PVS floating license

Category: Custom IC Design

By sjeur

$usertype
•
updated over 6 years ago by Andrew Beckett

6 replies • 17496 views
Discussion

Design migration tool

Category: Custom IC Design

By Faizan UL HAQ

$usertype
•
updated over 6 years ago by Andrew Beckett

21 replies • 42589 views
Discussion

Error during ADE spectre simulation

Category: Custom IC Design

By NorNand

$usertype
•
updated over 6 years ago by NorNand

12 replies • 23768 views
Discussion

DC OP calculation for voltage reference with Startup Circuit

Category: Custom IC Design

By Johanny Saenz

$usertype
•
updated over 6 years ago by FormerMember

3 replies • 17265 views
Discussion

Trouble using pPar with Spectre simulation

Category: Custom IC Design

By AlexandreBoyer

$usertype
•
updated over 6 years ago by Andrew Beckett

4 replies • 18122 views
Discussion

AMS simulation error after removing a verilogA cell from the testbench

Category: Custom IC Design

By RFStuff

$usertype
•
updated over 6 years ago by RFStuff

3 replies • 14740 views
Discussion

Verilog $random seems to be not random

Category: Custom IC Design

By HoWei

$usertype
•
updated over 6 years ago by Andrew Beckett

2 replies • 19173 views
Discussion

Unable to descend into any of the views defined in the view list, 'auCdl schematic'

Category: Custom IC Design

By musabfarooq

$usertype
•
updated over 6 years ago by Andrew Beckett

1 replies • 5456 views
Discussion

Dots instead of solid lines when plotting corners

Category: Custom IC Design

By Roman K

$usertype
•
updated over 6 years ago by FormerMember

1 replies • 15558 views
Discussion

Unreasonable numbers and contributors seen in ADE-L Spectre noise summary

Category: Custom IC Design

By mmVivek

$usertype
•
updated over 6 years ago by mmVivek

2 replies • 15191 views
Discussion

Post-Layout Simulation without front-end files of I/O cells

Category: Custom IC Design

By JavadBa

$usertype
•
started over 6 years ago

0 replies • 441 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.