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Custom IC Design

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  • Discussion

    Veriloga Montecarlo input from spectre

    Category: Custom IC Design

    By jeffreyprin

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    updated over 11 years ago by Andrew Beckett

    1 replies • 13083 views
  • Discussion

    Monte carlo on a verilog A custom macro model based on device instance not subckt instance

    Category: Custom IC Design

    By Fabb

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    •

    updated over 11 years ago by Andrew Beckett

    1 replies • 14404 views
  • Discussion

    How do I turn off flighlines from the bulk of transistors....

    Category: Custom IC Design

    By pham777

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    updated over 11 years ago by Andrew Beckett

    1 replies • 12944 views
  • Discussion

    Component Display parameter missing in EDIT menu Cadence 6.1.6-64b

    Category: Custom IC Design

    By sasuke

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    •

    updated over 11 years ago by Marc Heise

    1 replies • 15510 views
  • Discussion

    Pins, Nets created are not visible

    Category: Custom IC Design

    By Prash123

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    •

    updated over 11 years ago by Andrew Beckett

    1 replies • 13606 views
  • Discussion

    Timestamp.....

    Category: Custom IC Design

    By pham777

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    •

    updated over 11 years ago by aflex

    2 replies • 13155 views
  • Discussion

    Reading a data file in Veriloga code

    Category: Custom IC Design

    By Sali

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    •

    updated over 11 years ago by Sali

    4 replies • 17136 views
  • Discussion

    help on using diode model in Spectre simulation

    Category: Custom IC Design

    By apple419

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    updated over 11 years ago by Andrew Beckett

    2 replies • 17181 views
  • Discussion

    saving verilog-a triggers compilation instead of just syntax check

    Category: Custom IC Design

    By danmc

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    •

    updated over 11 years ago by danmc

    2 replies • 13315 views
  • Discussion

    sweep variable "bs" in hb, then use VAR("bs") in output expression, not plot in ADEXL

    Category: Custom IC Design

    By Taoni

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    updated over 11 years ago by Andrew Beckett

    6 replies • 7060 views
  • Discussion

    Strange behavior of traponly method (MMSIM/SpectreRF)

    Category: Custom IC Design

    By norrin

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    updated over 11 years ago by Frank Wiedmann

    2 replies • 11322 views
  • Discussion

    issue with (* cds_inherited_parameter *)

    Category: Custom IC Design

    By Fabb

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    •

    updated over 11 years ago by Fabb

    4 replies • 14511 views
  • Discussion

    How to use calculator to process a set of curves in wavescan

    Category: Custom IC Design

    By bjstroll

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    •

    updated over 11 years ago by Andrew Beckett

    1 replies • 15276 views
  • Discussion

    Extraction AS/AD in Assura RCX

    Category: Custom IC Design

    By TiNat

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    updated over 11 years ago by Andrew Beckett

    1 replies • 687 views
  • Discussion

    ocean -nograph error

    Category: Custom IC Design

    By nigam214

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    •

    updated over 11 years ago by Andrew Beckett

    6 replies • 3517 views
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