Custom IC Design

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Discussion

Writing out .lib & lef from virtuoso

Category: Custom IC Design

By Shameel

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updated over 11 years ago by Alex Soyer

5 replies • 5657 views
Discussion

schematic editor question: tie two global signals together

Category: Custom IC Design

By apple419

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updated over 11 years ago by apple419

4 replies • 17088 views
Discussion

Automatic schematic generation using SKILL

Category: Custom IC Design

By shamore

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updated over 11 years ago by dmay

10 replies • 22282 views
Discussion

Post data process of Monte Carlo SImulation Result

Category: Custom IC Design

By bhl3302

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started over 12 years ago

0 replies • 13142 views
Discussion

How to create a symbol from cdl netlist

Category: Custom IC Design

By pham777

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started over 12 years ago

0 replies • 13487 views
Discussion

extracted view simulation in OCEAN

Category: Custom IC Design

By Alex Vasjanov

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updated over 12 years ago by Alex Vasjanov

3 replies • 13898 views
Discussion

ADEXL retry test

Category: Custom IC Design

By pdub

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updated over 12 years ago by pdub

2 replies • 13686 views
Discussion

Simulation/work folder

Category: Custom IC Design

By HamidKhatibi

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updated over 12 years ago by HamidKhatibi

4 replies • 3088 views
Discussion

strmin error (XSTRM-1048)

Category: Custom IC Design

By danmc

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updated over 12 years ago by danmc

4 replies • 14597 views
Discussion

settings for Verilog Import

Category: Custom IC Design

By navi2582

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updated over 12 years ago by Andrew Beckett

1 replies • 14173 views
Discussion

query on spectre-MDL

Category: Custom IC Design

By santosh acc

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updated over 12 years ago by Andrew Beckett

1 replies • 13409 views
Discussion

mmsim72: licensing issue

Category: Custom IC Design

By iamlearning

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updated over 12 years ago by Andrew Beckett

6 replies • 17566 views
Discussion

Running PSS for an oscillator with a driving signal in some other part of the circuit.

Category: Custom IC Design

By RFStuff

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updated over 12 years ago by Andrew Beckett

5 replies • 15506 views
Discussion

How to pass parameters to a VerilogA module

Category: Custom IC Design

By RFStuff

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updated over 12 years ago by RFStuff

2 replies • 16168 views
Discussion

noisefile in a vdc source modeled by Verilog-A

Category: Custom IC Design

By Aldo2

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updated over 12 years ago by Aldo2

3 replies • 15671 views

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