Custom IC Design

Latest Posts

Discussion

leHiMarkNet check if net is already marked

Category: Custom IC Design

By beschorn

$usertype
•
updated over 10 years ago by CadSolution

2 replies • 14094 views
Discussion

Diva - LVS with Hierarchical extraction

Category: Custom IC Design

By djca

$usertype
•
started over 10 years ago

0 replies • 1336 views
Discussion

Probing bulk currents in Transistors

Category: Custom IC Design

By PhilipN

$usertype
•
updated over 10 years ago by ALfrg

1 replies • 13926 views
Discussion

Need a quick explanation for back annotating parasitics in IC6.1.4

Category: Custom IC Design

By bnugent

$usertype
•
updated over 10 years ago by Soroosh

10 replies • 18311 views
Discussion

Macromodel of a Current Steering DAC with ideal switches

Category: Custom IC Design

By zaratustra

$usertype
•
updated over 10 years ago by zaratustra

2 replies • 15624 views
Discussion

extracting jitter from an eye diagram

Category: Custom IC Design

By svilen

$usertype
•
updated over 10 years ago by Andrew Beckett

3 replies • 19280 views
Discussion

Simulating a logic library (without schematic views) in spectre

Category: Custom IC Design

By JohnB70

$usertype
•
updated over 10 years ago by Andrew Beckett

9 replies • 17042 views
Discussion

Noise margin analysis of a differential circuit

Category: Custom IC Design

By sazjad

$usertype
•
started over 10 years ago

0 replies • 13871 views
Discussion

Plotting Subcircuit Voltages

Category: Custom IC Design

By hoodskier

$usertype
•
updated over 10 years ago by FormerMember

1 replies • 15043 views
Discussion

Convergence issues with switched capacitor dc-dc converter

Category: Custom IC Design

By Aushickman

$usertype
•
updated over 10 years ago by FormerMember

1 replies • 18044 views
Discussion

Assura LVS SYNTAX ERROR

Category: Custom IC Design

By Zdeno

$usertype
•
updated over 10 years ago by Andrew Beckett

3 replies • 14797 views
Discussion

Use of array inside a loop in SPECTRE

Category: Custom IC Design

By wang159

$usertype
•
updated over 10 years ago by Andrew Beckett

1 replies • 14797 views
Discussion

How to remove Nets (guide lines) by wires (paths) in layout (virtuoso)?

Category: Custom IC Design

By Majid Rafei

$usertype
•
updated over 10 years ago by Majid Rafei

2 replies • 17860 views
Discussion

Delete all wires and vias

Category: Custom IC Design

By Majid Rafei

$usertype
•
updated over 10 years ago by Majid Rafei

2 replies • 16450 views
Discussion

Link matlab to cadence

Category: Custom IC Design

By syafiq

$usertype
•
updated over 10 years ago by Andrew Beckett

1 replies • 14089 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.