Custom IC Design

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Discussion

How to plot Id-Vg at different channel length by cadence spectre ?

Category: Custom IC Design

By richardyuan

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updated over 10 years ago by Andrew Beckett

7 replies • 17325 views
Discussion

Unable to generate Proper Layouts

Category: Custom IC Design

By SHEKHARvnit

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updated over 10 years ago by Andrew Beckett

6 replies • 14537 views
Discussion

One testbench for different analysis (dc, trans,...)

Category: Custom IC Design

By marten

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updated over 10 years ago by marten

2 replies • 15076 views
Discussion

How can I automate noise margin calculation ?

Category: Custom IC Design

By marten

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updated over 10 years ago by marten

11 replies • 23554 views
Discussion

performance & processor time

Category: Custom IC Design

By IAmAries

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updated over 10 years ago by Andrew Beckett

1 replies • 637 views
Discussion

QRC Substrate Technology Characterization: buried oxide layer?

Category: Custom IC Design

By anla

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updated over 10 years ago by Andrew Beckett

1 replies • 13369 views
Discussion

Why Vt-Channel Length curve differs from Short Channel Effect?

Category: Custom IC Design

By richardyuan

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updated over 10 years ago by Andrew Beckett

3 replies • 14761 views
Discussion

QRC and newer Assura

Category: Custom IC Design

By analogy

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updated over 10 years ago by Andrew Beckett

1 replies • 13992 views
Discussion

nmrd?

Category: Custom IC Design

By IAmAries

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updated over 10 years ago by IAmAries

6 replies • 14837 views
Discussion

Howto integrate OCEAN measurement into ADE XL Monte Carlo analysis

Category: Custom IC Design

By marten

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updated over 10 years ago by marten

1 replies • 13216 views
Discussion

data processing in Cadence

Category: Custom IC Design

By Sali

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started over 10 years ago

0 replies • 13226 views
Discussion

*Warning* (DB-220704) : The Pcell super master : lf150rf_lib/ResistorUnit/layout is not a SKILL super master

Category: Custom IC Design

By Sss19

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updated over 10 years ago by ColinSutlieff

5 replies • 4478 views
Discussion

Current probing

Category: Custom IC Design

By analogy

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updated over 10 years ago by Andrew Beckett

1 replies • 17148 views
Discussion

Output Signal is not plotted in the ADEXL environment

Category: Custom IC Design

By afridimcci

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updated over 10 years ago by FormerMember

1 replies • 16836 views
Discussion

Regarding addition of .sp file to a analogLib model

Category: Custom IC Design

By eashwar g

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updated over 10 years ago by eashwar g

4 replies • 16178 views

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