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Custom IC Design

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  • Discussion

    How to change save state default setup?

    Category: Custom IC Design

    By archive archive

    •

    updated over 14 years ago by archive

    2 replies • 14379 views
  • Discussion

    missing dollarEqualParams in capacitor subckt in auCdl netlist

    Category: Custom IC Design

    By Paulux Paulux

    •

    started over 14 years ago

    0 replies • 13025 views
  • Discussion

    Virtuoso freezes when loading old state with ADE-L

    Category: Custom IC Design

    By vivkr vivkr

    •

    updated over 14 years ago by Andrew Beckett

    1 replies • 14020 views
  • Discussion

    auCdl netlist subckt missing parameters

    Category: Custom IC Design

    By Paulux Paulux

    •

    updated over 14 years ago by Paulux

    4 replies • 15406 views
  • Discussion

    APS: AC during TRAN option ignored

    Category: Custom IC Design

    By vivkr vivkr

    •

    updated over 14 years ago by vivkr

    2 replies • 13005 views
  • Discussion

    Save and Check in IC61

    Category: Custom IC Design

    By minci minci

    •

    updated over 14 years ago by Andrew Beckett

    1 replies • 13047 views
  • Discussion

    default simulation states when using ADE-L

    Category: Custom IC Design

    By vivkr vivkr

    •

    updated over 14 years ago by vivkr

    2 replies • 14572 views
  • Discussion

    ADE-XL error

    Category: Custom IC Design

    By pitter pitter

    •

    updated over 14 years ago by Andrew Beckett

    1 replies • 16347 views
  • Discussion

    Looking for a way to alter VT function

    Category: Custom IC Design

    By MarkSummers MarkSummers

    •

    updated over 14 years ago by MarkSummers

    1 replies • 13337 views
  • Discussion

    Help in research

    Category: Custom IC Design

    By MarkCohen231 MarkCohen231

    •

    updated over 14 years ago by Andrew Beckett

    1 replies • 569 views
  • Discussion

    how does APS handle 0-V DC sources? Is iprobe better?

    Category: Custom IC Design

    By vivkr vivkr

    •

    updated over 14 years ago by Andrew Beckett

    3 replies • 13083 views
  • Discussion

    Continuing transient analysis

    Category: Custom IC Design

    By StreamCX StreamCX

    •

    updated over 14 years ago by StreamCX

    2 replies • 6012 views
  • Discussion

    Verilog Import

    Category: Custom IC Design

    By engSemi engSemi

    •

    started over 14 years ago

    0 replies • 13046 views
  • Discussion

    vhdl behavioral code to schematic conversion in cadence

    Category: Custom IC Design

    By pmuppala pmuppala

    •

    updated over 14 years ago by Andrew Beckett

    3 replies • 14020 views
  • Discussion

    Using VI-style Command line editing in OCEAN?

    Category: Custom IC Design

    By leddedup leddedup

    •

    updated over 14 years ago by Andrew Beckett

    1 replies • 12986 views
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