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Custom IC Design

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  • Discussion

    Problem in creating logic to electrical connect module in verilogams

    Category: Custom IC Design

    By indra0804 indra0804

    •

    started over 12 years ago

    0 replies • 14411 views
  • Discussion

    Problem while running verilog-ams block in cadence schematic editor

    Category: Custom IC Design

    By indra0804 indra0804

    •

    updated over 12 years ago by indra0804

    2 replies • 15131 views
  • Discussion

    Initial condition in subcircuit

    Category: Custom IC Design

    By MaK78 MaK78

    •

    updated over 12 years ago by MaK78

    3 replies • 16738 views
  • Discussion

    Charge Pump output Capacitance

    Category: Custom IC Design

    By Mushir Mushir

    •

    updated over 12 years ago by Andrew Beckett

    8 replies • 16655 views
  • Discussion

    How to resolve xstreamout (IC 6.1) , it pop you to save cellview ?

    Category: Custom IC Design

    By Charley Chen Charley Chen

    •

    updated over 12 years ago by Andrew Beckett

    3 replies • 13318 views
  • Discussion

    DC sweep with ams simulator ?

    Category: Custom IC Design

    By isazulkc isazulkc

    •

    updated over 12 years ago by isazulkc

    2 replies • 13460 views
  • Discussion

    ELC problem: simulation failed with the status 512

    Category: Custom IC Design

    By Digital84 Digital84

    •

    updated over 12 years ago by Digital84

    2 replies • 13468 views
  • Discussion

    How to use frequency in calculator when doing AC Sweep in Virtuoso

    Category: Custom IC Design

    By nonlocality nonlocality

    •

    updated over 12 years ago by Andrew Beckett

    1 replies • 24929 views
  • Discussion

    How to change analysis type in Ocean?

    Category: Custom IC Design

    By Honghao Honghao

    •

    updated over 12 years ago by Honghao

    2 replies • 13737 views
  • Discussion

    IC61 Custom Digital Placer skill for rows calculation

    Category: Custom IC Design

    By Eduard Raines Eduard Raines

    •

    updated over 12 years ago by Andrew Beckett

    3 replies • 13113 views
  • Discussion

    Ultrasim is not recognising hspice (<) syntax

    Category: Custom IC Design

    By Ankumar15 Ankumar15

    •

    updated over 12 years ago by Andrew Beckett

    1 replies • 872 views
  • Discussion

    Any way to use ADE variables in Hierarchy Editor ?

    Category: Custom IC Design

    By kentauta kentauta

    •

    updated over 12 years ago by kentauta

    2 replies • 13495 views
  • Discussion

    utsoi model for spectre?

    Category: Custom IC Design

    By huber huber

    •

    updated over 12 years ago by huber

    2 replies • 13218 views
  • Discussion

    Opening layout view opens schematic view

    Category: Custom IC Design

    By egolowen egolowen

    •

    updated over 12 years ago by Andrew Beckett

    3 replies • 14339 views
  • Discussion

    How to plot the verilogA module data points using OCEAN

    Category: Custom IC Design

    By RFStuff RFStuff

    •

    updated over 12 years ago by Andrew Beckett

    9 replies • 15914 views
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