Custom IC Design

Latest Posts

Discussion

getting rid of little informational text on mpps

Category: Custom IC Design

By linbo
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updated over 13 years ago by linbo

3 replies • 13388 views
Discussion

Writing simulation data into a file after running

Category: Custom IC Design

By Medya
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updated over 13 years ago by Andrew Beckett

1 replies • 12985 views
Discussion

ADE XL: default x axis for plots

Category: Custom IC Design

By keble6
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updated over 13 years ago by keble6

2 replies • 13773 views
Discussion

Parameterized VHDL using generics and ADE-AMS simulation

Category: Custom IC Design

By lperktold
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started over 13 years ago

0 replies • 13323 views
Discussion

get first pole from PZ analysis

Category: Custom IC Design

By Rainer123
•
updated over 13 years ago by Rainer123

4 replies • 13623 views
Discussion

Generate Clones does not work

Category: Custom IC Design

By tyanata
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updated over 13 years ago by tyanata

2 replies • 13863 views
Discussion

DC Match Over Corners

Category: Custom IC Design

By BVT1
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started over 13 years ago

0 replies • 13100 views
Discussion

How to translate netlist with subcircuits into top-level subcircuit?

Category: Custom IC Design

By TiNat
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updated over 13 years ago by skillUser

1 replies • 6442 views
Discussion

Assura LVS error (cell expanded), need help debugging the error !!

Category: Custom IC Design

By SivaChaitanya
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updated over 13 years ago by SivaChaitanya

1 replies • 16685 views
Discussion

Howto read port currents when having multi-terminal bus ports in VerilogA ?

Category: Custom IC Design

By Herge
•
updated over 13 years ago by Herge

6 replies • 15599 views
Discussion

How to debug VerilogA compilation when code seems to check clean but simulation aborts when compiling ?

Category: Custom IC Design

By Herge
•
updated over 13 years ago by Herge

3 replies • 14982 views
Discussion

montecarlo simulations beetween Wmin and Wmax for mos transistors

Category: Custom IC Design

By inessadm
•
updated over 13 years ago by inessadm

2 replies • 13387 views
Discussion

Working with tabs in virtuoso schematic editor (opus 6.1.5 - ADE L)

Category: Custom IC Design

By Aldo2
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updated over 13 years ago by Aldo2

7 replies • 4229 views
Discussion

Virtuoso: "save a copy" from read-only cell in 6.1.4 but not in 6.1.5

Category: Custom IC Design

By StefanSL
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updated over 13 years ago by StefanSL

2 replies • 1195 views
Discussion

automatically spacing and aligning instances in Virtuoso schematic editor

Category: Custom IC Design

By MOSFET
•
updated over 13 years ago by Andrew Beckett

1 replies • 17075 views

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