Custom IC Design

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Discussion

can we ask virtuoso to write its lock or CDS.log somewhere else than $HOME ?

Category: Custom IC Design

By ebecheto

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updated 1 month ago by Andrew Beckett

4 replies • 1479 views
Discussion

Weird simulation results in latest Spectre Transient Noise Simulation RAK

Category: Custom IC Design

By OPump

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started 1 month ago

0 replies • 717 views
Discussion

calculator expression to compare wreal value with voltage value

Category: Custom IC Design

By Monica123

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updated 1 month ago by Monica123

2 replies • 1436 views
Discussion

Having Maestro report what DSPF view it used for each simulation

Category: Custom IC Design

By Mohsen2

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started 1 month ago

0 replies • 580 views
Discussion

ibis2subck for IBIS circuit doesn't extract analogmodel

Category: Custom IC Design

By JoseDuarte

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started 1 month ago

0 replies • 618 views
Discussion

I am not able to select the layer while drawing a wire or a bus in Layout.

Category: Custom IC Design

By skillEater

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updated 1 month ago by RobMan

1 replies • 1079 views
Discussion

How to mute WARNING This OS does not appear to be a Cadence supported Linux configuration

Category: Custom IC Design

By ebecheto

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updated 1 month ago by Andrew Beckett

1 replies • 1022 views
Discussion

Modgen: How to add dummy FETs sharing diffusion without issues of marker layers?

Category: Custom IC Design

By sceekr

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started 1 month ago

0 replies • 1206 views
Discussion

gsclib090 (gpdk090 standard cell library) download?

Category: Custom IC Design

By GS202507021424

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updated 1 month ago by RobMan

1 replies • 1533 views
Discussion

Problem with ADE Explorer and spectre_encrypt (IC 21.1 ISR22)

Category: Custom IC Design

By GL202502244954

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started 1 month ago

0 replies • 1239 views
Discussion

Using VCSV File in Spectre Simulation

Category: Custom IC Design

By aalbason

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updated 1 month ago by aalbason

2 replies • 1993 views
Discussion

Quantus PVS Parasitic Extraction ERROR (LBRCXM-992)

Category: Custom IC Design

By RV202509139743

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started 1 month ago

0 replies • 1009 views
Discussion

Maestro ERROR for bus ">" when plot signals

Category: Custom IC Design

By LH202509171654

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started 1 month ago

0 replies • 586 views
Discussion

Effect of Large Voltage (1 MV) on Accuracy When Using relref=sigglobal in Spectre APS/X

Category: Custom IC Design

By ycyang

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started 1 month ago

0 replies • 799 views
Discussion

Missing instance on LVS (IOs)

Category: Custom IC Design

By RV202509139743

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started 1 month ago

0 replies • 1041 views

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