Custom IC Design

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Discussion

Mixer Stability

Category: Custom IC Design

By TobyK

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started over 1 year ago

0 replies • 3571 views
Discussion

How to set the stress conditions in a reliability analysis in ADE explorer?

Category: Custom IC Design

By unSkilled

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updated over 1 year ago by JankoK

1 replies • 4325 views
Discussion

Library Manager - open terminal option on right clicking any cell or views

Category: Custom IC Design

By firebolt3

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updated over 1 year ago by firebolt3

4 replies • 2142 views
Discussion

The so called "Virtuoso Layout Suite EXL"

Category: Custom IC Design

By Restart

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updated over 1 year ago by Restart

8 replies • 4114 views
Discussion

output file i.e. tran.tran.tran as different name

Category: Custom IC Design

By Kashfi

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updated over 1 year ago by Kashfi

2 replies • 4070 views
Discussion

Extract the list of devices used in the layout

Category: Custom IC Design

By Vishesh Gupta

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updated over 1 year ago by Vishesh Gupta

2 replies • 4101 views
Discussion

Meaning of 1v in pmos_1v in gpdk045 library

Category: Custom IC Design

By APM

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updated over 1 year ago by APM

3 replies • 4647 views
Discussion

Gate Operator Control Panel

Category: Custom IC Design

By shyam Bharvad

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updated over 1 year ago by Andrew Beckett

1 replies • 3645 views
Discussion

Fetching the operating point of a transistor in VerilogA with "$simprobe" always returns 0

Category: Custom IC Design

By CroAndro

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updated over 1 year ago by CroAndro

2 replies • 1083 views
Discussion

Inherited terminal

Category: Custom IC Design

By Vishesh Gupta

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updated over 1 year ago by Vishesh Gupta

4 replies • 6037 views
Discussion

Re-run Monte Carlo failures for Two-Step trim simulations

Category: Custom IC Design

By TempViator

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updated over 1 year ago by TempViator

1 replies • 4221 views
Discussion

FATAL (SPECTRE-20): Illegal instruction: seems something wrong addressing S-parameter

Category: Custom IC Design

By RogerChen

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updated over 1 year ago by RogerChen

2 replies • 5030 views
Discussion

How to override the default values using Verilog netlist.

Category: Custom IC Design

By Omar Ghazal

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updated over 1 year ago by Omar Ghazal

4 replies • 5013 views
Discussion

simulating quadrature oscillator

Category: Custom IC Design

By soroush7492

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started over 1 year ago

0 replies • 3655 views
Discussion

Excluding Devices from Quantus RC Extraction

Category: Custom IC Design

By sgcad

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started over 1 year ago

0 replies • 3730 views

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