Custom IC Design

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verilog Syntax errors not highlighted in text editor

Category: Custom IC Design

By JavierC

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updated 2 months ago by JavierC

6 replies • 1731 views
Discussion

Loading *WARNING* Connection to MACHINE failed. Connection refused

Category: Custom IC Design

By hesaliveJim

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updated 3 months ago by hesaliveJim

4 replies • 1117 views
Discussion

Any major difference between Cadence Advanced Node GPDK v1.0 and v1.1 release?

Category: Custom IC Design

By hesaliveJim

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updated 3 months ago by hesaliveJim

1 replies • 923 views
Discussion

best way to integrate different calibre extraction corners to virtuoso ADE

Category: Custom IC Design

By micipici

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updated 3 months ago by Andrew Beckett

1 replies • 916 views
Discussion

Distributed simulations

Category: Custom IC Design

By OPump

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updated 3 months ago by OPump

1 replies • 884 views
Discussion

Automatic routing --> All nets in Layout GXL of Cadence Virtuoso

Category: Custom IC Design

By HN20250717689

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started 3 months ago

0 replies • 293 views
Discussion

How to plot a histogram of a relative error in a Monte Carlo analysis?

Category: Custom IC Design

By DomiHammerfall

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updated 3 months ago by DomiHammerfall

3 replies • 1182 views
Discussion

Unable to run Monte-Carlo simulation on ADE-XL

Category: Custom IC Design

By rtyuy

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updated 3 months ago by rtyuy

32 replies • 4076 views
Discussion

Error doing in Local Optimization in ADE Assembler

Category: Custom IC Design

By Bakr Abdelgaliel

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updated 3 months ago by Bakr Abdelgaliel

2 replies • 983 views
Discussion

spectre assert

Category: Custom IC Design

By Joe Mellon

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updated 3 months ago by Joe Mellon

2 replies • 1115 views
Discussion

Follow Up Discussion on Maestro can't save current with "WARNING (ADE-1063): The output with same signal '***' is already defined."

Category: Custom IC Design

By Kelsey Reed

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updated 3 months ago by Kelsey Reed

1 replies • 344 views
Discussion

How do I set default layout view for EM/IR data layout analysis Lib/Cell/View

Category: Custom IC Design

By BillH314

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started 3 months ago

0 replies • 215 views
Discussion

The drain and source is different direction in pex with different fingers of the same mos

Category: Custom IC Design

By dogman4

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updated 3 months ago by Andrew Beckett

1 replies • 965 views
Discussion

The current direction is different after simulation with different fingers of the same mos

Category: Custom IC Design

By dogman4

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updated 3 months ago by dogman4

3 replies • 1255 views
Discussion

Generate steamOut.map for Innovus GDS export in Virtuoso?

Category: Custom IC Design

By Gurjot Singh

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updated 3 months ago by Andrew Beckett

1 replies • 1020 views

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