Custom IC Design

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Methodology for Sweeping Vth (delvto) or Defining Sigma Corners for DAC Mismatch Analysis?

Category: Custom IC Design

By VP202511202051

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updated 24 days ago by VP202511202051

1 replies • 498 views
Discussion

Exceeded the blowup limit when running Monte Carlo analysis

Category: Custom IC Design

By aalbason

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updated 24 days ago by aalbason

3 replies • 549 views
Discussion

I am encountering an issue where EMX cannot read or display Metal 8 and Metal 9 layers in the layout view. Metal 6 appears correctly.

Category: Custom IC Design

By SA202511121933

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updated 25 days ago by Andrew Beckett

3 replies • 840 views
Discussion

simulation from dspf Netlist

Category: Custom IC Design

By SA202503313913

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started 25 days ago

0 replies • 307 views
Discussion

Pass touchstone file path as string parameter to n2port instance

Category: Custom IC Design

By MarkyMark

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updated 27 days ago by Andrew Beckett

1 replies • 392 views
Discussion

recovered transient simulation shows different waveform

Category: Custom IC Design

By an wx

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started 28 days ago

0 replies • 373 views
Discussion

Pnoise analysis with windowed sampling

Category: Custom IC Design

By ULPAnalog

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started 29 days ago

0 replies • 404 views
Discussion

fft function in the calculator is missing

Category: Custom IC Design

By kolep

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updated 1 month ago by Andrew Beckett

1 replies • 442 views
Discussion

Unable to update the number of MC point on the Run Plan

Category: Custom IC Design

By kolep

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updated 1 month ago by Andrew Beckett

1 replies • 457 views
Discussion

Virtuoso AMS NOUNIT error with Xcelium - Not caching libraries

Category: Custom IC Design

By AS202502163432

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updated 1 month ago by AS202502163432

8 replies • 1050 views
Discussion

Recovering "actionable" netlist from GDS II

Category: Custom IC Design

By GS202507021424

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updated 1 month ago by GS202507021424

6 replies • 597 views
Discussion

How to reference multiple PWL waveforms from a single file in Spectre (vsource type=pwl)

Category: Custom IC Design

By baltaci

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updated 1 month ago by Andrew Beckett

1 replies • 465 views
Discussion

Copy schematic/symbol views hierarchically

Category: Custom IC Design

By ycau

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updated 1 month ago by Andrew Beckett

2 replies • 398 views
Discussion

Transfer design variable from schematic / layout to av_extracted view

Category: Custom IC Design

By FM202408077836

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updated 1 month ago by Andrew Beckett

2 replies • 585 views
Discussion

Explanation of stb analysis results YG, YL, ZG, and ZL

Category: Custom IC Design

By Frank Wiedmann

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started 1 month ago

0 replies • 485 views

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