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Custom IC Design

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  • Discussion

    Can harmonic balance load-pull tests be run in parallel?

    Category: Custom IC Design

    By MatthewLove

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    started over 6 years ago

    0 replies • 13555 views
  • Discussion

    Bindkey to activate PVS-DRC/LVS

    Category: Custom IC Design

    By sjwprc

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    •

    updated over 6 years ago by Andrew Beckett

    3 replies • 2393 views
  • Discussion

    Importing standard cell area into .lib file automatically.

    Category: Custom IC Design

    By Barani7302

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    •

    updated over 6 years ago by Guangjun Cao

    1 replies • 15562 views
  • Discussion

    Measurements Across Corners

    Category: Custom IC Design

    By Boyan

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    •

    started over 6 years ago

    0 replies • 13954 views
  • Discussion

    spectre save command - usage

    Category: Custom IC Design

    By roopakvasa

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    •

    updated over 6 years ago by Andrew Beckett

    1 replies • 4003 views
  • Discussion

    Generating Device In Schematic From Layout

    Category: Custom IC Design

    By FormerMember

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    •

    updated over 6 years ago by Andrew Beckett

    1 replies • 2901 views
  • Discussion

    how to load skill script in the icrp without .cdsinit

    Category: Custom IC Design

    By YiWang

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    •

    updated over 6 years ago by YiWang

    2 replies • 15638 views
  • Discussion

    Quantus: warning regarding separate field solver techfile with MEOL stack description

    Category: Custom IC Design

    By dontpanic

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    •

    updated over 6 years ago by dontpanic

    2 replies • 14199 views
  • Discussion

    QRC: extraction fails due to ports names including the "+" character

    Category: Custom IC Design

    By dontpanic

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    •

    updated over 6 years ago by dontpanic

    2 replies • 2095 views
  • Discussion

    Import Schematic from Mentor Tanner to Cadence

    Category: Custom IC Design

    By HwDoesThisWork

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    •

    updated over 6 years ago by Andrew Beckett

    10 replies • 19697 views
  • Discussion

    Liberate - Custom Cell Characterization

    Category: Custom IC Design

    By manpmanp

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    •

    updated over 6 years ago by anurans

    1 replies • 2160 views
  • Discussion

    Plotting transistor parameters in a temperature sweep

    Category: Custom IC Design

    By CADcasualty

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    •

    updated over 6 years ago by CADcasualty

    2 replies • 16782 views
  • Discussion

    Fix "tool tip" colors in GNOME

    Category: Custom IC Design

    By dontpanic

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    •

    updated over 6 years ago by dontpanic

    2 replies • 2715 views
  • Discussion

    how to setup connectivity between layout and schematic

    Category: Custom IC Design

    By Amit yadav

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    •

    updated over 6 years ago by skillUser

    1 replies • 17275 views
  • Discussion

    VerilogA parsing problem

    Category: Custom IC Design

    By StanleyN

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    •

    updated over 6 years ago by subramanya007

    4 replies • 17711 views
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