Custom IC Design

Latest Posts

Discussion

Can university users use https://support.cadence.com website?

Category: Custom IC Design

By wangyunxin
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updated over 1 year ago by Andrew Beckett

1 replies • 866 views
Discussion

Equation based Sparameters

Category: Custom IC Design

By ChrisTower
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started over 1 year ago

0 replies • 4139 views
Discussion

Using extracted view with iterated instance

Category: Custom IC Design

By Mathieu Chene
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updated over 1 year ago by Mathieu Chene

2 replies • 5013 views
Discussion

Creating vector variable in ADE XL to configure Verilog-A module

Category: Custom IC Design

By RaffaeleUdS
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updated over 1 year ago by Andrew Beckett

1 replies • 4736 views
Discussion

Any way to set a default value for the design variables in ADE explorer

Category: Custom IC Design

By jason1127
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updated over 1 year ago by Andrew Beckett

1 replies • 4732 views
Discussion

Previously closed windows minimize upon reopening in IC23.10

Category: Custom IC Design

By LMendolia
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updated over 1 year ago by Andrew Beckett

1 replies • 4811 views
Discussion

How to repair miscalculated bBox of an object that I cannot spot on the layout?

Category: Custom IC Design

By MichalWolodzko
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updated over 1 year ago by MichalWolodzko

2 replies • 4804 views
Discussion

Simulation temerature dependent on DC power

Category: Custom IC Design

By Martinsh
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updated over 1 year ago by ShawnLogan

7 replies • 5786 views
Discussion

Cadence Layout DRC Pins Error

Category: Custom IC Design

By Sarah1898
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updated over 1 year ago by ShawnLogan

4 replies • 6719 views
Discussion

Align hierarchic pins in layout with SKILL script.

Category: Custom IC Design

By MichalWolodzko
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started over 1 year ago

0 replies • 4409 views
Discussion

scaling and DBU/UU - XStream vs XOasis

Category: Custom IC Design

By vshih
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updated over 1 year ago by Andrew Beckett

1 replies • 1282 views
Discussion

How to setup monte-carlo run for variation analysis in virtuoso

Category: Custom IC Design

By supriyo1985
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updated over 1 year ago by Andrew Beckett

1 replies • 5016 views
Discussion

XNOR Gate Operation Issue in Cadence

Category: Custom IC Design

By Maria98
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updated over 1 year ago by Maria98

2 replies • 5517 views
Discussion

Format/Syntax for Writing Aged Model Files for Reliability Simulations

Category: Custom IC Design

By rahulsingh
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updated over 1 year ago by rahulsingh

6 replies • 2560 views
Discussion

[Solved] Cannot Direct Plot PAC Current (Even though it is saved in outputs!)

Category: Custom IC Design

By MahdiMohammadi
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updated over 1 year ago by MahdiMohammadi

2 replies • 5566 views

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