Custom IC Design

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Discussion

Transfer design variable from schematic / layout to av_extracted view

Category: Custom IC Design

By FM202408077836

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updated 1 month ago by Andrew Beckett

2 replies • 592 views
Discussion

Explanation of stb analysis results YG, YL, ZG, and ZL

Category: Custom IC Design

By Frank Wiedmann

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started 1 month ago

0 replies • 490 views
Discussion

Question on integrated noise in PNOISE (sampled) Noise summary

Category: Custom IC Design

By Yuto Lau

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updated 1 month ago by Yuto Lau

4 replies • 774 views
Discussion

Automating Layout Cell Updates Using SKILL with Cell List from File

Category: Custom IC Design

By AR202509246930

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updated 1 month ago by Andrew Beckett

1 replies • 595 views
Discussion

plotting results does not properly work

Category: Custom IC Design

By TommasoF

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updated 1 month ago by TommasoF

8 replies • 1135 views
Discussion

Query regarding Virtuoso EMX tool

Category: Custom IC Design

By VLSI lab IITB

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updated 1 month ago by VLSI lab IITB

4 replies • 896 views
Discussion

about cadence virtuoso guidance manual problem

Category: Custom IC Design

By JJ202503031042

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updated 1 month ago by JJ202503031042

3 replies • 794 views
Discussion

Creating Assura DRC rule to check that sep of 2 layers is exactly 2 different values

Category: Custom IC Design

By Miguel V

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started 1 month ago

0 replies • 467 views
Discussion

LVS Warning: “Unattached port label” for PLUS/MINUS on layer ind11_text — can’t locate device

Category: Custom IC Design

By RK202509013321

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updated 1 month ago by RobMan

3 replies • 744 views
Discussion

Dual Core Oscillator Open Loop

Category: Custom IC Design

By IS20250922772

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started 1 month ago

0 replies • 438 views
Discussion

Assembler: possible to disable automatic evaluation of output expressions?

Category: Custom IC Design

By dontpanic

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updated 1 month ago by Andrew Beckett

1 replies • 574 views
Discussion

Assembler: possible to force inclusion of model file(s) at the very beginning of netlist?

Category: Custom IC Design

By dontpanic

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updated 1 month ago by Andrew Beckett

3 replies • 653 views
Discussion

Interactive mode for Spectre using Python/TCL

Category: Custom IC Design

By CB202409064221

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updated 1 month ago by Andrew Beckett

1 replies • 335 views
Discussion

PAC is giving 0V at the output

Category: Custom IC Design

By SA202512302438

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updated 1 month ago by Frank Wiedmann

2 replies • 726 views
Discussion

Replace symbol pin names without changing the pin placement and symbol boundary

Category: Custom IC Design

By SimhanAnalog

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updated 1 month ago by SimhanAnalog

4 replies • 1248 views

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