Custom IC Design

Latest Posts

Discussion

How to read in a text file separated by delays in Verilog A. They delays are relative and to be read from the text file?

Category: Custom IC Design

By Nisharg shah

$usertype
•
started over 3 years ago

0 replies • 7702 views
Discussion

Simple example/template for a (matrix based, if possible) schematic pcell

Category: Custom IC Design

By SteveVrk

$usertype
•
updated over 3 years ago by SteveVrk

3 replies • 2290 views
Discussion

Accessing analog voltages in hierarchy from Verilog AMS

Category: Custom IC Design

By amacSS

$usertype
•
updated over 3 years ago by amacSS

4 replies • 10126 views
Discussion

use of calcVal() to access expressions from other tests

Category: Custom IC Design

By AncisMichele

$usertype
•
updated over 3 years ago by AncisMichele

4 replies • 18660 views
Discussion

2x1 mux Shorted Internal Nets lvs error

Category: Custom IC Design

By ehdwns48

$usertype
•
started over 3 years ago

0 replies • 8273 views
Discussion

Netlister's subcircuit naming convention

Category: Custom IC Design

By ZoltanT

$usertype
•
updated over 3 years ago by lchensd

8 replies • 4234 views
Discussion

Drawing an Elongated Ellipse Shape

Category: Custom IC Design

By Ynishant

$usertype
•
updated over 3 years ago by Ynishant

2 replies • 8733 views
Discussion

DRC Flat Hierarchical Errors

Category: Custom IC Design

By Kevin Buck

$usertype
•
started over 3 years ago

0 replies • 7616 views
Discussion

CDF Parameter not found

Category: Custom IC Design

By SuminJ

$usertype
•
updated over 3 years ago by Andrew Beckett

1 replies • 8369 views
Discussion

ViVA: How how to save all pictures quickly?

Category: Custom IC Design

By StephanWeber

$usertype
•
updated over 3 years ago by StephanWeber

2 replies • 8082 views
Discussion

How to get windowID of Skill IDE?

Category: Custom IC Design

By Kevin Li

$usertype
•
updated over 3 years ago by Kevin Li

2 replies • 8137 views
Discussion

Retaining group membership when copying fig group objects with "Transparent Group" set to "ON"

Category: Custom IC Design

By Jeff Lucas

$usertype
•
updated over 3 years ago by Andrew Beckett

1 replies • 1367 views
Discussion

HOW TO CALCULATE CLOCK FREQUENCY OF VPWL VOLTAGE SOURCE

Category: Custom IC Design

By rijalomkar

$usertype
•
updated over 3 years ago by Andrew Beckett

1 replies • 7928 views
Discussion

Ignoring instances in the layout during LVS (and/or DRC)

Category: Custom IC Design

By delgsy

$usertype
•
updated over 3 years ago by Andrew Beckett

4 replies • 5697 views
Discussion

AMS simulation fails to generate netlist

Category: Custom IC Design

By Yongqi Hu

$usertype
•
updated over 3 years ago by Yongqi Hu

9 replies • 12599 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.