Custom IC Design

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Using saved corners by spectre in AMS simulator

Category: Custom IC Design

By MonaG

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updated over 4 years ago by Andrew Beckett

1 replies • 11527 views
Discussion

DC Sweep multiple variables at same time

Category: Custom IC Design

By MaHa255

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updated over 4 years ago by Andrew Beckett

1 replies • 15500 views
Discussion

harmonic balance for down-converting mixers

Category: Custom IC Design

By dzakharian

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updated over 4 years ago by dzakharian

9 replies • 14731 views
Discussion

how to define actime_pair = yes

Category: Custom IC Design

By sjwprcker

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updated over 4 years ago by Andrew Beckett

3 replies • 12178 views
Discussion

Import Netlist to Schematic with existing Cells in other Libraries

Category: Custom IC Design

By FormerMember

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updated over 4 years ago by Andrew Beckett

5 replies • 13943 views
Discussion

sampling a digital bus

Category: Custom IC Design

By maaz2020

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updated over 4 years ago by maaz2020

4 replies • 13207 views
Discussion

Probing All Currents in ADE Explorer / XL Without Inserting Components or Manual Selection

Category: Custom IC Design

By life

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updated over 4 years ago by Andrew Beckett

4 replies • 14047 views
Discussion

Stability analysis with hbstb

Category: Custom IC Design

By BakBeh

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updated over 4 years ago by BakBeh

5 replies • 14218 views
Discussion

Problem in doing pss pnoise simulation to get PFD CP output current noise

Category: Custom IC Design

By macanfeng11

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updated over 4 years ago by Andrew Beckett

6 replies • 15801 views
Discussion

How to mark a floating bus net as noConn in Schematic Composer in IC5141

Category: Custom IC Design

By RFStuff

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updated over 4 years ago by Andrew Beckett

6 replies • 21570 views
Discussion

Techgen Error: Starting Triangle not defined

Category: Custom IC Design

By CasV

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updated over 4 years ago by CasV

4 replies • 12646 views
Discussion

The Principle of Automatic Sweeping

Category: Custom IC Design

By Matsuge

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updated over 4 years ago by Matsuge

4 replies • 14764 views
Discussion

Convergence issue with Verilog-A model

Category: Custom IC Design

By AQoutb

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updated over 4 years ago by Andrew Beckett

4 replies • 16185 views
Discussion

Variable set in corners overrides variable locally defined in test

Category: Custom IC Design

By SteveDobbs

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updated over 4 years ago by Andrew Beckett

4 replies • 13140 views
Discussion

Virtuoso schematic set net to default to a certain color

Category: Custom IC Design

By CSCNalu

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updated over 4 years ago by Andrew Beckett

3 replies • 14246 views

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