Custom IC Design

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Measuring Operating Point Parameters in Stacked-FET Devices

Category: Custom IC Design

By Conorp

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updated over 5 years ago by Andrew Beckett

3 replies • 16409 views
Discussion

spectre warnings

Category: Custom IC Design

By siva123

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updated over 5 years ago by monglebest

2 replies • 16520 views
Discussion

Finding gain of stage 1 in 2 stage opamp using stb analysis

Category: Custom IC Design

By AmoghD

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updated over 5 years ago by FormerMember

8 replies • 17820 views
Discussion

ERROR - DB-270000 - Invalid String Index - Cannot Open for Read or Edit a Cell

Category: Custom IC Design

By life

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updated over 5 years ago by Andrew Beckett

1 replies • 4134 views
Discussion

Group as parametric set is not working

Category: Custom IC Design

By cADEUser

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updated over 5 years ago by Andrew Beckett

3 replies • 15079 views
Discussion

EMX integrated inside Virtuoso

Category: Custom IC Design

By sidm

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updated over 5 years ago by Andrew Beckett

3 replies • 15753 views
Discussion

Copying layout from cell to other cell issue

Category: Custom IC Design

By Senan

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started over 5 years ago

0 replies • 13241 views
Discussion

Getting/highlighting all input pins of a design in schematic

Category: Custom IC Design

By SunnyB

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updated over 5 years ago by Andrew Beckett

3 replies • 4082 views
Discussion

Different files formats needed for a complete IC and package design and verification flow

Category: Custom IC Design

By sidm

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updated over 5 years ago by Alex9

3 replies • 13768 views
Discussion

Re: Environment variables to source from $home/.cadence/dfII

Category: Custom IC Design

By slim15

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updated over 5 years ago by Andrew Beckett

1 replies • 1906 views
Discussion

Gray/Grey schematic for easier viewing of highlighted nets

Category: Custom IC Design

By CADcasualty

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updated over 5 years ago by CADcasualty

5 replies • 3434 views
Discussion

Changing single transistor instance parameters via SKILL

Category: Custom IC Design

By KevinWarren

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updated over 5 years ago by KevinWarren

2 replies • 14596 views
Discussion

Fatal error when use ADE L to simulate veriloga blocks.

Category: Custom IC Design

By HaolinCong

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updated over 5 years ago by HaolinCong

11 replies • 19130 views
Discussion

ModGen routing problem in Cadence Virtuoso

Category: Custom IC Design

By Senan

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updated over 5 years ago by Senan

2 replies • 15312 views
Discussion

Netlist Extraction

Category: Custom IC Design

By Phuong Truong

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updated over 5 years ago by Andrew Beckett

1 replies • 15592 views

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