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Custom IC Design

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  • Discussion

    Simulation issue with ideal relay implemented in verilog a

    Category: Custom IC Design

    By lahsivece

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    updated over 6 years ago by Andrew Beckett

    4 replies • 16790 views
  • Discussion

    can't edit value of CDF parameters in Edit Object Property form

    Category: Custom IC Design

    By Nhumai

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    updated over 6 years ago by Andrew Beckett

    4 replies • 6865 views
  • Discussion

    SCH1285: cannot instantiate abstracrt view as it has no symbol or scematic

    Category: Custom IC Design

    By aviyadav

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    updated over 6 years ago by aviyadav

    4 replies • 15542 views
  • Discussion

    Using custom VHDL library in cadence VHDL-AMS

    Category: Custom IC Design

    By RFStuff

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    updated over 6 years ago by RFStuff

    11 replies • 23876 views
  • Discussion

    Explicitely selecting dimension of signals

    Category: Custom IC Design

    By itos

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    started over 6 years ago

    0 replies • 12830 views
  • Discussion

    OP annotate problem with Config based sim

    Category: Custom IC Design

    By DavidLou

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    started over 6 years ago

    0 replies • 12665 views
  • Discussion

    How to plot value of dynamic parameter during Transient analysis

    Category: Custom IC Design

    By Boyan

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    updated over 6 years ago by Andrew Beckett

    1 replies • 16818 views
  • Discussion

    Simulation doesn't run without AMAP folder

    Category: Custom IC Design

    By zaratustra

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    updated over 6 years ago by zaratustra

    2 replies • 2059 views
  • Discussion

    dcmatch mth=1m is not working

    Category: Custom IC Design

    By Kakhandaki

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    updated over 6 years ago by Kakhandaki

    2 replies • 778 views
  • Discussion

    how to custom abutted devices' poly to contact distance

    Category: Custom IC Design

    By DavidLou

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    updated over 6 years ago by Andrew Beckett

    3 replies • 2405 views
  • Discussion

    simulation of Short circuit condition in parallel plate capacitor

    Category: Custom IC Design

    By NorNand

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    updated over 6 years ago by Andrew Beckett

    1 replies • 13416 views
  • Discussion

    how to map a layout done in layout-L to layoyt-xl

    Category: Custom IC Design

    By RFStuff

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    •

    updated over 6 years ago by Andrew Beckett

    1 replies • 12914 views
  • Discussion

    Library Re-characterization Guide

    Category: Custom IC Design

    By anurans

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    •

    updated over 6 years ago by anurans

    6 replies • 16026 views
  • Discussion

    Characterizing library for emerging 2DFETs with in-house .va based models

    Category: Custom IC Design

    By nt2612

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    updated over 6 years ago by Guangjun Cao

    3 replies • 15934 views
  • Discussion

    how to set input slew and load in template with Liberate for characterization

    Category: Custom IC Design

    By fengye

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    updated over 6 years ago by fengye

    4 replies • 16383 views
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