Custom IC Design

Latest Posts

Discussion

DC run and Transient Response in Cadence ADE

Category: Custom IC Design

By FMRLI
•
updated over 10 years ago by Andrew Beckett

1 replies • 13725 views
Discussion

Is it safe to ignore the checklimit warnings?

Category: Custom IC Design

By dogrush
•
updated over 10 years ago by Andrew Beckett

1 replies • 14431 views
Discussion

Standard Cell Substrate Contacts

Category: Custom IC Design

By Jordan Morris
•
updated over 10 years ago by Quek

1 replies • 16000 views
Discussion

Diva and Conic Sides

Category: Custom IC Design

By djca
•
updated over 10 years ago by Andrew Beckett

1 replies • 13167 views
Discussion

==create Netlist fail for modified av Extracted view==

Category: Custom IC Design

By tomchen
•
updated over 10 years ago by Andrew Beckett

2 replies • 14132 views
Discussion

Substrate extraction

Category: Custom IC Design

By Rade
•
updated over 10 years ago by fielddev

5 replies • 15779 views
Discussion

Questions on Verilog-XL structural schematic bottom-up flow

Category: Custom IC Design

By Lynks
•
started over 10 years ago

0 replies • 12624 views
Discussion

LVS versus physical Verilog from Encounter, Power Node Mismatch

Category: Custom IC Design

By Kabal
•
updated over 10 years ago by Hypnus

6 replies • 16291 views
Discussion

Problem Photodiode modelling in Verilog-A

Category: Custom IC Design

By papy07
•
updated over 10 years ago by ahmdd

5 replies • 15600 views
Discussion

Replacing Via1 to Via2 per Bindkey in IC5.1

Category: Custom IC Design

By Laur9
•
updated over 10 years ago by Guruprasad S

11 replies • 18163 views
Discussion

Digital Pot: MOS as a logic switch

Category: Custom IC Design

By ctayers
•
updated over 10 years ago by ctayers

5 replies • 15496 views
Discussion

Schematic and layout with multiple power pins

Category: Custom IC Design

By naveiitb
•
updated over 10 years ago by naveiitb

4 replies • 19374 views
Discussion

Warnings for Breakdowns, not suppressing.

Category: Custom IC Design

By MarkGr15
•
updated over 10 years ago by Andrew Beckett

4 replies • 16488 views
Discussion

How to make MIM cap model LVS clean

Category: Custom IC Design

By Casp
•
updated over 10 years ago by Quek

1 replies • 14047 views
Discussion

Assura DRC errors - UMC 90nm

Category: Custom IC Design

By GURU M
•
updated over 10 years ago by Quek

5 replies • 6040 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.