Digital Implementation

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Clock Tree Latency Calculation Difference between reportClockTree & report_timing

Category: Digital Implementation

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updated over 17 years ago by archive

4 replies • 11540 views
Discussion

About GCELLGRID and TRACK Statement in DEF

Category: Digital Implementation

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updated over 17 years ago by archive

5 replies • 17169 views
Discussion

encounter and conformal

Category: Digital Implementation

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started over 17 years ago

0 replies • 13302 views
Discussion

Is it a MUST to use capTable to do .13um design?

Category: Digital Implementation

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updated over 17 years ago by archive

5 replies • 15082 views
Discussion

NanoRoute CRASH, need help.....VERSION SOC-E 52 Update 5

Category: Digital Implementation

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updated over 17 years ago by archive

1 replies • 13773 views
Discussion

Is there any approach to add global power net despite DesignImport pwoer tab?

Category: Digital Implementation

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started over 17 years ago

0 replies • 13356 views
Discussion

long wire transition time issues

Category: Digital Implementation

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updated over 17 years ago by archive

14 replies • 20063 views
Discussion

A warning when doing timing-driven NanoRoute, Urgent!

Category: Digital Implementation

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updated over 17 years ago by archive

4 replies • 14730 views
Discussion

no new cells at top level

Category: Digital Implementation

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updated over 17 years ago by archive

3 replies • 14351 views
Discussion

Ideal nets in ETS

Category: Digital Implementation

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started over 17 years ago

0 replies • 13422 views
Discussion

how to the error "Size of cell PADI45(80000,141660) is not an integer multiple of its site IOSite(20,400000)"

Category: Digital Implementation

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updated over 17 years ago by archive

1 replies • 638 views
Discussion

LVS after place&route may fail due to clock tree buffers

Category: Digital Implementation

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$usertype
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updated over 17 years ago by archive

4 replies • 1970 views
Discussion

Using a PSpice advanced part into a subcircuit

Category: Digital Implementation

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updated over 17 years ago by NewYorkSteve

1 replies • 13732 views
Discussion

avoid use of certain cells within a subdesign

Category: Digital Implementation

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updated over 17 years ago by archive

1 replies • 13886 views
Discussion

how could FE extract coupled C when doing timeDesign?

Category: Digital Implementation

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updated over 17 years ago by archive

3 replies • 14172 views

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