Digital Implementation

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Discussion

addRing creating rings outside design boundary

Category: Digital Implementation

By TA202503121730
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started 3 days ago

0 replies • 81 views
Discussion

gsclib045 data sheet available?

Category: Digital Implementation

By FG202508072745
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started 15 days ago

0 replies • 219 views
Discussion

Issue about using SkyWater130 and Genus

Category: Digital Implementation

By SR202412023415
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started 24 days ago

0 replies • 329 views
Discussion

Residual power in whole design vs summed gate groups in Joules, even with full instance coverage

Category: Digital Implementation

By SR202412023415
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started 26 days ago

0 replies • 329 views
Discussion

DRC Violations due to Macro Placement and Power Straps in Innovus Stylus Flow

Category: Digital Implementation

By XL202501136611
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started 1 month ago

0 replies • 433 views
Discussion

How to manage block-level and top-level SDC constraints?

Category: Digital Implementation

By MichR
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started 1 month ago

0 replies • 492 views
Discussion

Min Pulse Width Violation

Category: Digital Implementation

By SG20250716916
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started 1 month ago

0 replies • 506 views
Discussion

Congestion at Routing Stage

Category: Digital Implementation

By SG20250716916
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started 1 month ago

0 replies • 457 views
Discussion

Foundation flow stylus

Category: Digital Implementation

By VK20250620161
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started 1 month ago

0 replies • 524 views
Discussion

INNOVUS: connect internal power nets between hard macros

Category: Digital Implementation

By PK202501238151
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started 1 month ago

0 replies • 555 views
Discussion

Tracing Gates to RTL Modules and Line Numbers in Flattened Netlist with Genus

Category: Digital Implementation

By SR202412023415
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started 2 months ago

0 replies • 703 views
Discussion

Synthesizing Specific Gates in Cadence Genus

Category: Digital Implementation

By SR202412023415
•
updated 2 months ago by SR202412023415

2 replies • 1229 views
Discussion

Cadence Genus: Submodule synthesis and reuse and integrate it in top module

Category: Digital Implementation

By XH202505277146
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started 2 months ago

0 replies • 951 views
Discussion

in VSVN netlist getting error , i am using mlcv swicth

Category: Digital Implementation

By SM20250402327
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updated 3 months ago by SM20250402327

1 replies • 971 views
Discussion

Glitch in Synthesized Netlist Simulation of SR Latch — Occurs Only in One Instance

Category: Digital Implementation

By SaranyaBalan
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started 3 months ago

0 replies • 1200 views

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