Digital Implementation

Latest Posts

Discussion

how to give "user define compare points" in "non-equivalent database" in conformal LEC?

Category: Digital Implementation

By GoIn
•
started over 9 years ago

0 replies • 1176 views
Discussion

Listing All Modules And Blocks In Innovus Using dbGet.

Category: Digital Implementation

By thannasantosh
•
updated over 9 years ago by khandaker

1 replies • 22446 views
Discussion

deciding insertion delay and clock skew.

Category: Digital Implementation

By gops
•
updated over 9 years ago by jagadishbvn

2 replies • 30526 views
Discussion

addRing per side net order

Category: Digital Implementation

By drdanmc
•
started over 9 years ago

0 replies • 14431 views
Discussion

Understanding Innovus' hold analysis in a hierarchical design flow utilizing hard macros

Category: Digital Implementation

By marten
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started over 9 years ago

0 replies • 5322 views
Discussion

path name

Category: Digital Implementation

By nhanle
•
started over 9 years ago

0 replies • 14237 views
Discussion

Deleting multiple selected Insts in encounter

Category: Digital Implementation

By Erudite
•
updated over 9 years ago by khandaker

1 replies • 15291 views
Discussion

Error in starting guiMainForm.tcl

Category: Digital Implementation

By ImanKian
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started over 9 years ago

0 replies • 14229 views
Discussion

AC limit fixing in Innovus - what data is needed in the ICT (and hence compiled qrcTech) files?

Category: Digital Implementation

By Brighty
•
updated over 9 years ago by badhriu

1 replies • 1740 views
Discussion

clock tree synthesis for clock gating

Category: Digital Implementation

By quiet
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updated over 9 years ago by shiva anala

7 replies • 21125 views
Discussion

clock gating paths

Category: Digital Implementation

By maven7783
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updated over 9 years ago by shiva anala

12 replies • 32441 views
Discussion

how max_sink_trans value is going to affect the timing of my design

Category: Digital Implementation

By gops
•
updated over 9 years ago by GBHASKAR

4 replies • 16060 views
Discussion

set_dont_touch_network on clock

Category: Digital Implementation

By Chith
•
updated over 9 years ago by fitz

1 replies • 16609 views
Discussion

Conflict between bus notation in Verilog ('[ ]') and Cadence ('< >')

Category: Digital Implementation

By palubid71
•
updated over 9 years ago by Kari

3 replies • 7946 views
Discussion

non-default report

Category: Digital Implementation

By fitz
•
started over 9 years ago

0 replies • 14441 views

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