• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Functional Verification
CDNS - double leaderboard script

Functional Verification

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Latest Posts

  • Create a new Post
  • Discussion

    Pass string to $system in SystemVerilog?

    Category: Functional Verification

    By archive archive

    •

    updated over 18 years ago by archive

    3 replies • 18546 views
  • Discussion

    SV transaction sequence dependency constraint?

    Category: Functional Verification

    By archive archive

    •

    updated over 18 years ago by archive

    5 replies • 15063 views
  • Discussion

    uRM task-level interface?

    Category: Functional Verification

    By archive archive

    •

    updated over 18 years ago by archive

    3 replies • 13518 views
  • Discussion

    compile SystemVerilog and Verilog separately?

    Category: Functional Verification

    By archive archive

    •

    updated over 18 years ago by archive

    8 replies • 18127 views
  • Discussion

    Creating fifo channel between class objects

    Category: Functional Verification

    By archive archive

    •

    updated over 18 years ago by archive

    1 replies • 14941 views
  • Discussion

    Three new SystemVerilog EZ-Start appnotes and code examples

    Category: Functional Verification

    By archive archive

    •

    updated over 18 years ago by archive

    1 replies • 13167 views
  • Discussion

    Clocking Block assignment bug in IUS583?

    Category: Functional Verification

    By archive archive

    •

    updated over 18 years ago by archive

    2 replies • 14163 views
  • Discussion

    What is wrong with this code ? I'm trying to use a Queue of classes..

    Category: Functional Verification

    By archive archive

    •

    updated over 18 years ago by archive

    2 replies • 1397 views
  • Discussion

    Poor SystemVerilog Support in NC?

    Category: Functional Verification

    By archive archive

    •

    updated over 18 years ago by archive

    7 replies • 16045 views
  • Discussion

    ncsim out-of-memory when enabling code coverage

    Category: Functional Verification

    By archive archive

    •

    updated over 18 years ago by archive

    5 replies • 15827 views
  • Discussion

    Using Artisan standard cells in Verilog??

    Category: Functional Verification

    By archive archive

    •

    started over 18 years ago

    0 replies • 12823 views
  • Discussion

    keeping rst asserted n clocks into the proof

    Category: Functional Verification

    By archive archive

    •

    updated over 18 years ago by archive

    2 replies • 13388 views
  • Discussion

    modeling a constraint for a signal that is only high once (ever)

    Category: Functional Verification

    By archive archive

    •

    updated over 18 years ago by archive

    5 replies • 14182 views
  • Discussion

    Property transformations

    Category: Functional Verification

    By archive archive

    •

    updated over 18 years ago by archive

    3 replies • 13630 views
  • Discussion

    multiple binding (star configuration) of method/event port

    Category: Functional Verification

    By archive archive

    •

    updated over 18 years ago by archive

    2 replies • 1264 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information