Functional Verification

Latest Posts

Discussion

comments in the files list -> possible ?

Category: Functional Verification

By amnldm

$usertype
•
updated over 2 years ago by amnldm

3 replies • 3717 views
Discussion

Xcelium's xcelium.d directory

Category: Functional Verification

By amnldm

$usertype
•
updated over 2 years ago by StephenH

1 replies • 2659 views
Discussion

How attach/detach windows in SimVision?

Category: Functional Verification

By amnldm

$usertype
•
updated over 2 years ago by StephenH

1 replies • 1519 views
Discussion

Extract FSM explicity

Category: Functional Verification

By snitkau

$usertype
•
updated over 2 years ago by StephenH

1 replies • 7208 views
Discussion

Memory Viewer formatting

Category: Functional Verification

By HardDiskJockey

$usertype
•
updated over 2 years ago by carloscrum

1 replies • 7702 views
Discussion

xrun slow snapshot loading

Category: Functional Verification

By alexek

$usertype
•
updated over 2 years ago by alexek

4 replies • 9196 views
Discussion

Merging the coverage will overwrite the covergroup reports?

Category: Functional Verification

By akagamisg

$usertype
•
updated over 2 years ago by StephenH

1 replies • 6684 views
Discussion

Debugging constraints with tcl interactive debug mode

Category: Functional Verification

By chetan somana

$usertype
•
updated over 2 years ago by chetan somana

7 replies • 10314 views
Discussion

Is it possible to connect two workspace/simulations via DPI-C?

Category: Functional Verification

By mxlusereight

$usertype
•
updated over 2 years ago by StephenH

1 replies • 1406 views
Discussion

Free version of NC-Verilog

Category: Functional Verification

By Daniel Figueiredo

$usertype
•
updated over 2 years ago by StephenH

3 replies • 8854 views
Discussion

Irun error MXINDR with a verilog PLL model wrapper written in VHDL, any way to workaround?

Category: Functional Verification

By mxlusereight

$usertype
•
updated over 2 years ago by mxlusereight

2 replies • 7310 views
Discussion

How to Map covergroup from present regression database to a reference vPlan

Category: Functional Verification

By Rolly

$usertype
•
updated over 2 years ago by StephenH

1 replies • 7339 views
Discussion

Xcelium waveform dump into custom directory

Category: Functional Verification

By DamianRRR

$usertype
•
updated over 2 years ago by StephenH

1 replies • 9726 views
Discussion

System Verilog: always @( * ) is not working, but explicit declaration always @( s1, s1, s3) is working

Category: Functional Verification

By HoWei

$usertype
•
updated over 2 years ago by HoWei

5 replies • 13251 views
Discussion

Jaspergold -- Net does not have a driver

Category: Functional Verification

By Vivek Kakkireni

$usertype
•
updated over 2 years ago by ErikSeligman

1 replies • 2765 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.