Functional Verification

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Discussion

How do I exclude my CPU netlist from probe?

Category: Functional Verification

By Ncsim User 1
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updated over 6 years ago by Ncsim User 1

2 replies • 14075 views
Discussion

Puzzled by definition of this struct

Category: Functional Verification

By TaoZ
•
updated over 6 years ago by TaoZ

2 replies • 13510 views
Discussion

What's the definition and the function of value()

Category: Functional Verification

By TaoZ
•
updated over 6 years ago by TaoZ

2 replies • 1683 views
Discussion

What could be the reason of *E,DLCSMD error?

Category: Functional Verification

By Jeff000
•
updated over 7 years ago by Tudor Timi

1 replies • 5808 views
Discussion

DLCSMD Errors

Category: Functional Verification

By Chris Hopkins
•
updated over 7 years ago by cmarqu42

8 replies • 27911 views
Discussion

How to show posedges by Simvision expression?

Category: Functional Verification

By Jeff000
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updated over 7 years ago by Jeff000

2 replies • 3137 views
Discussion

How to list connections for a wire?

Category: Functional Verification

By Jeff000
•
started over 7 years ago

0 replies • 581 views
Discussion

Fork a task with parameter from within a function

Category: Functional Verification

By Jeff000
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updated over 7 years ago by StephenH

3 replies • 1599 views
Discussion

parametrized cover class instance mapping in vplan

Category: Functional Verification

By yoshiko
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started over 7 years ago

0 replies • 12677 views
Discussion

AMS Netlister Error: "Illegal non-local reference to constant function [10.3.5(IEEE)]"

Category: Functional Verification

By Abel Ace
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started over 7 years ago

0 replies • 776 views
Discussion

SDF back annotation in systemVerilog design using interfaces

Category: Functional Verification

By arash1902
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started over 7 years ago

0 replies • 14147 views
Discussion

Where can I ask tools question on Synopsys VCS simulator?

Category: Functional Verification

By Ncsim User 1
•
started over 7 years ago

0 replies • 13464 views
Discussion

xrun timing check

Category: Functional Verification

By FormerMember
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updated over 7 years ago by cmarqu42

1 replies • 4644 views
Discussion

NC-Verilog user manual

Category: Functional Verification

By anmos
•
updated over 7 years ago by StephenH

3 replies • 35023 views
Discussion

Replace "`includes" with in-line modules - NC-Verilog

Category: Functional Verification

By anmos
•
updated over 7 years ago by anmos

1 replies • 5440 views

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