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Functional Verification

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  • Discussion

    Missing symbols in UCIS shared library

    Category: Functional Verification

    By Abdulhamid Abdulhamid

    •

    updated over 9 years ago by StephenH

    1 replies • 13112 views
  • Discussion

    bind procedure doesn't work if target VHDL unit is from a library

    Category: Functional Verification

    By Marius Ciurea Marius Ciurea

    •

    started over 9 years ago

    0 replies • 1418 views
  • Discussion

    how can i dump depth 1 level by $shm_probe

    Category: Functional Verification

    By JBPARK JBPARK

    •

    started over 9 years ago

    0 replies • 13179 views
  • Discussion

    Several entity/architecture pairs for the the same cell?

    Category: Functional Verification

    By LuisGutierrez LuisGutierrez

    •

    started over 9 years ago

    0 replies • 431 views
  • Discussion

    Color highlighting SimVision's console

    Category: Functional Verification

    By freitas freitas

    •

    updated over 9 years ago by Doug Koslow

    3 replies • 2734 views
  • Discussion

    Viewing Verilog Tasks in Simvision

    Category: Functional Verification

    By tcatkins tcatkins

    •

    updated over 9 years ago by tcatkins

    1 replies • 14374 views
  • Discussion

    compilation error

    Category: Functional Verification

    By chandanc11 chandanc11

    •

    started over 9 years ago

    0 replies • 12731 views
  • Discussion

    Any alternative way to connect an internal DUT's signals to TB's interface's modport?

    Category: Functional Verification

    By Rama Kishore Rama Kishore

    •

    updated over 9 years ago by Rama Kishore

    2 replies • 6571 views
  • Discussion

    IRUN command to change the Assertion severity level

    Category: Functional Verification

    By mahee424 mahee424

    •

    updated over 9 years ago by StephenH

    5 replies • 18784 views
  • Discussion

    cover property evaluation error

    Category: Functional Verification

    By mahee424 mahee424

    •

    updated over 9 years ago by mahee424

    2 replies • 14046 views
  • Discussion

    Query regarding the usage of analog assertions in systemverilog file

    Category: Functional Verification

    By susanta susanta

    •

    updated over 9 years ago by tpylant

    6 replies • 16095 views
  • Discussion

    Redirect Spectre results to buffer

    Category: Functional Verification

    By Khenglish Khenglish

    •

    updated over 9 years ago by Khenglish

    2 replies • 13367 views
  • Discussion

    Running Multiple Test Cases back to back (Regression)

    Category: Functional Verification

    By lijoostenk lijoostenk

    •

    started over 9 years ago

    0 replies • 13974 views
  • Discussion

    ERROR : Object found for name dut.register but language domain is not supported !!

    Category: Functional Verification

    By zoombarabar zoombarabar

    •

    updated over 9 years ago by zoombarabar

    4 replies • 16563 views
  • Discussion

    Regression Testing in UVM

    Category: Functional Verification

    By Eliz Eliz

    •

    updated over 9 years ago by Eliz

    2 replies • 16446 views
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