Functional Verification

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Discussion

How do I map signal values to meaningful string in simvision?

Category: Functional Verification

By avidanefody

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updated over 4 years ago by avidanefody

4 replies • 16445 views
Discussion

Question: How to use -incdir with reg_verifier

Category: Functional Verification

By Amr Saleem

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updated over 4 years ago by StephenH

1 replies • 2184 views
Discussion

forcing the creation of a vcd file

Category: Functional Verification

By freitas

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updated over 4 years ago by rkaur9

14 replies • 34270 views
Discussion

Enable probes via tcl script at certain time or event

Category: Functional Verification

By Pedro P

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updated over 4 years ago by StephenH

1 replies • 11897 views
Discussion

$fscanf: reading a file and extracting a particular word or string or args

Category: Functional Verification

By MaheshKumar

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started over 4 years ago

0 replies • 11788 views
Discussion

make xcellium process command display only uvm processes?

Category: Functional Verification

By avidanefody

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updated over 4 years ago by StephenH

4 replies • 12601 views
Discussion

Xcelium Functional Coverage

Category: Functional Verification

By Sparsh Gupta

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updated over 4 years ago by StephenH

6 replies • 36324 views
Discussion

Functional Coverage using IMC

Category: Functional Verification

By sriganeshd

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updated over 4 years ago by mukukr

6 replies • 28332 views
Discussion

System Verilog Functional Coverage using NCSIM

Category: Functional Verification

By ndalia

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updated over 4 years ago by mukukr

8 replies • 23801 views
Discussion

[vManager] Questions about Exclude options for Code coverage improvement

Category: Functional Verification

By vqnguyen

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updated over 4 years ago by vqnguyen

2 replies • 16251 views
Discussion

SV: How to name an unnamed block

Category: Functional Verification

By SysTom

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updated over 4 years ago by Brats

6 replies • 26746 views
Discussion

xmsim/BSSXCD = The element count of bit-stream has reached to a value that can cross the integer range in case anymore element gets added to bit-stream

Category: Functional Verification

By Nandeesha

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updated over 4 years ago by muffi

1 replies • 2522 views
Discussion

probe tcl syntax to save variables inside automatic tasks in systemverilog

Category: Functional Verification

By dtodorov

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updated over 4 years ago by StephenH

2 replies • 14770 views
Discussion

Fresh Incisive installation using IScape

Category: Functional Verification

By musazal

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updated over 4 years ago by musazal

4 replies • 13316 views
Discussion

Simvision: xmsim: *E,TRRANGEC: range constraint violation

Category: Functional Verification

By quantumion

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updated over 4 years ago by StephenH

1 replies • 4463 views

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