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Functional Verification

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  • Discussion

    Create Functional Verilog from Schematic.

    Category: Functional Verification

    By anmos

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    updated over 7 years ago by anmos

    6 replies • 22271 views
  • Discussion

    Unable to simulate Verilog Testbench - 'lic_error-18'

    Category: Functional Verification

    By anmos

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    updated over 7 years ago by anmos

    5 replies • 6276 views
  • Discussion

    How to use uvm_agent for sequencing

    Category: Functional Verification

    By Sporadic Crash

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    updated over 7 years ago by Sporadic Crash

    4 replies • 19979 views
  • Discussion

    Multi Dimensional Dynamic Array Constraint support Issue in System Verilog/UVM

    Category: Functional Verification

    By mahee424

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    updated over 7 years ago by mahee424

    3 replies • 3914 views
  • Discussion

    Multi Dimensional Dynamic Array Constraint support Issue in System Verilog/UVM

    Category: Functional Verification

    By mahee424

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    updated over 7 years ago by mahee424

    3 replies • 4922 views
  • Discussion

    Simvision Changes the Trace type of some signals on reinvoke

    Category: Functional Verification

    By snitkau

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    updated over 7 years ago by Doug Koslow

    1 replies • 17323 views
  • Discussion

    Time in Simvision's Expression calculator

    Category: Functional Verification

    By Tzachi Noy

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    updated over 7 years ago by evancox10

    5 replies • 9550 views
  • Discussion

    performance: constraints list of lists

    Category: Functional Verification

    By Gabv

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    started over 7 years ago

    0 replies • 13611 views
  • Discussion

    run_phase doesn't update SV interface signals

    Category: Functional Verification

    By Sporadic Crash

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    updated over 7 years ago by Sporadic Crash

    2 replies • 3221 views
  • Discussion

    IMC Coverage figures in ascii report differs from GUI & html report

    Category: Functional Verification

    By prkroon

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    started over 7 years ago

    0 replies • 3273 views
  • Discussion

    LVS filter pins in layout

    Category: Functional Verification

    By PietroUser

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    started over 7 years ago

    0 replies • 14271 views
  • Discussion

    Coverage not getting hit when trying with IUS simulator

    Category: Functional Verification

    By anikam

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    updated over 7 years ago by tpylant

    3 replies • 16055 views
  • Discussion

    How to read label inside a particular instance and check its connectivity with the label of another instance

    Category: Functional Verification

    By Garima M

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    updated over 7 years ago by Garima M

    4 replies • 15388 views
  • Discussion

    PSpice A/D Stuck in lite version even if I have a license dongle. How to switch ?

    Category: Functional Verification

    By ajeya

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    started over 7 years ago

    0 replies • 1382 views
  • Discussion

    Indago tcl commands

    Category: Functional Verification

    By anonms

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    started over 7 years ago

    0 replies • 15404 views
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