Functional Verification

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Discussion

DLCSMD Errors

Category: Functional Verification

By Chris Hopkins
•
updated over 8 years ago by cmarqu42

8 replies • 32346 views
Discussion

How to show posedges by Simvision expression?

Category: Functional Verification

By Jeff000
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updated over 8 years ago by Jeff000

2 replies • 3989 views
Discussion

How to list connections for a wire?

Category: Functional Verification

By Jeff000
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started over 8 years ago

0 replies • 813 views
Discussion

Fork a task with parameter from within a function

Category: Functional Verification

By Jeff000
•
updated over 8 years ago by StephenH

3 replies • 2281 views
Discussion

parametrized cover class instance mapping in vplan

Category: Functional Verification

By yoshiko
•
started over 8 years ago

0 replies • 14390 views
Discussion

AMS Netlister Error: "Illegal non-local reference to constant function [10.3.5(IEEE)]"

Category: Functional Verification

By Abel Ace
•
started over 8 years ago

0 replies • 1046 views
Discussion

SDF back annotation in systemVerilog design using interfaces

Category: Functional Verification

By arash1902
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started over 8 years ago

0 replies • 16042 views
Discussion

Where can I ask tools question on Synopsys VCS simulator?

Category: Functional Verification

By Ncsim User 1
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started over 8 years ago

0 replies • 16409 views
Discussion

xrun timing check

Category: Functional Verification

By FormerMember
•
updated over 8 years ago by cmarqu42

1 replies • 6293 views
Discussion

NC-Verilog user manual

Category: Functional Verification

By anmos
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updated over 8 years ago by StephenH

3 replies • 39284 views
Discussion

Replace "`includes" with in-line modules - NC-Verilog

Category: Functional Verification

By anmos
•
updated over 8 years ago by anmos

1 replies • 6331 views
Discussion

How to get the output from this button in Simvison(counts of edge, high/low time...) by tcl command?

Category: Functional Verification

By Jeff000
•
started over 8 years ago

0 replies • 1620 views
Discussion

ERROR: ncvlog: *E,EXPRLC (/file/hierarchy/**.sv,14|18): expecting a left brace ('{') [SystemVerilog]. (Prohibited pattern (?-xism:\*E,))

Category: Functional Verification

By khan2018
•
started over 8 years ago

0 replies • 1125 views
Discussion

Constraints for multidimensional array

Category: Functional Verification

By Egor
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updated over 8 years ago by Egor

2 replies • 18110 views
Discussion

How to remove multiple Markers quickly in Simvision?

Category: Functional Verification

By Jeff000
•
updated over 8 years ago by HariPrashanth

1 replies • 4341 views

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