Functional Verification

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Discussion

How to get the output from this button in Simvison(counts of edge, high/low time...) by tcl command?

Category: Functional Verification

By Jeff000
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started over 7 years ago

0 replies • 1222 views
Discussion

ERROR: ncvlog: *E,EXPRLC (/file/hierarchy/**.sv,14|18): expecting a left brace ('{') [SystemVerilog]. (Prohibited pattern (?-xism:\*E,))

Category: Functional Verification

By khan2018
•
started over 7 years ago

0 replies • 817 views
Discussion

Constraints for multidimensional array

Category: Functional Verification

By Egor
•
updated over 7 years ago by Egor

2 replies • 15749 views
Discussion

How to remove multiple Markers quickly in Simvision?

Category: Functional Verification

By Jeff000
•
updated over 7 years ago by HariPrashanth

1 replies • 3197 views
Discussion

Specman - init a param value of internal sequence (execute from another sequence) directly from test

Category: Functional Verification

By sara8
•
started over 7 years ago

0 replies • 872 views
Discussion

How to query if a database has been opened in Simvision with tcl command?

Category: Functional Verification

By Jeff000
•
updated over 7 years ago by cmarqu42

1 replies • 2195 views
Discussion

Using strings in constraints to randomize data

Category: Functional Verification

By PSAM
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updated over 7 years ago by PSAM

2 replies • 16039 views
Discussion

cannot pass uvm_sequence_item to send_to_dut

Category: Functional Verification

By Sporadic Crash
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updated over 7 years ago by TAM1

1 replies • 13181 views
Discussion

Create Functional Verilog from Schematic.

Category: Functional Verification

By anmos
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updated over 7 years ago by anmos

6 replies • 20447 views
Discussion

Unable to simulate Verilog Testbench - 'lic_error-18'

Category: Functional Verification

By anmos
•
updated over 7 years ago by anmos

5 replies • 5480 views
Discussion

How to use uvm_agent for sequencing

Category: Functional Verification

By Sporadic Crash
•
updated over 7 years ago by Sporadic Crash

4 replies • 17110 views
Discussion

Multi Dimensional Dynamic Array Constraint support Issue in System Verilog/UVM

Category: Functional Verification

By mahee424
•
updated over 7 years ago by mahee424

3 replies • 3331 views
Discussion

Multi Dimensional Dynamic Array Constraint support Issue in System Verilog/UVM

Category: Functional Verification

By mahee424
•
updated over 7 years ago by mahee424

3 replies • 4467 views
Discussion

Simvision Changes the Trace type of some signals on reinvoke

Category: Functional Verification

By snitkau
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updated over 7 years ago by Doug Koslow

1 replies • 15880 views
Discussion

Time in Simvision's Expression calculator

Category: Functional Verification

By Tzachi Noy
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updated over 7 years ago by evancox10

5 replies • 8563 views

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