Functional Verification

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NC-Verilog user manual

Category: Functional Verification

By anmos

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updated over 7 years ago by StephenH

3 replies • 36747 views
Discussion

Replace "`includes" with in-line modules - NC-Verilog

Category: Functional Verification

By anmos

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updated over 7 years ago by anmos

1 replies • 5745 views
Discussion

How to get the output from this button in Simvison(counts of edge, high/low time...) by tcl command?

Category: Functional Verification

By Jeff000

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started over 7 years ago

0 replies • 1376 views
Discussion

ERROR: ncvlog: *E,EXPRLC (/file/hierarchy/**.sv,14|18): expecting a left brace ('{') [SystemVerilog]. (Prohibited pattern (?-xism:\*E,))

Category: Functional Verification

By khan2018

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started over 7 years ago

0 replies • 905 views
Discussion

Constraints for multidimensional array

Category: Functional Verification

By Egor

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updated over 7 years ago by Egor

2 replies • 16650 views
Discussion

How to remove multiple Markers quickly in Simvision?

Category: Functional Verification

By Jeff000

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updated over 7 years ago by HariPrashanth

1 replies • 3470 views
Discussion

Specman - init a param value of internal sequence (execute from another sequence) directly from test

Category: Functional Verification

By sara8

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started over 7 years ago

0 replies • 938 views
Discussion

How to query if a database has been opened in Simvision with tcl command?

Category: Functional Verification

By Jeff000

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updated over 7 years ago by cmarqu42

1 replies • 2460 views
Discussion

Using strings in constraints to randomize data

Category: Functional Verification

By PSAM

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updated over 7 years ago by PSAM

2 replies • 16908 views
Discussion

cannot pass uvm_sequence_item to send_to_dut

Category: Functional Verification

By Sporadic Crash

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updated over 7 years ago by TAM1

1 replies • 13922 views
Discussion

Create Functional Verilog from Schematic.

Category: Functional Verification

By anmos

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updated over 7 years ago by anmos

6 replies • 21701 views
Discussion

Unable to simulate Verilog Testbench - 'lic_error-18'

Category: Functional Verification

By anmos

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updated over 7 years ago by anmos

5 replies • 6053 views
Discussion

How to use uvm_agent for sequencing

Category: Functional Verification

By Sporadic Crash

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updated over 7 years ago by Sporadic Crash

4 replies • 19295 views
Discussion

Multi Dimensional Dynamic Array Constraint support Issue in System Verilog/UVM

Category: Functional Verification

By mahee424

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updated over 7 years ago by mahee424

3 replies • 3732 views
Discussion

Multi Dimensional Dynamic Array Constraint support Issue in System Verilog/UVM

Category: Functional Verification

By mahee424

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updated over 7 years ago by mahee424

3 replies • 4784 views

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