Logic Design

Latest Posts

Discussion

report lower hierarchy level

Category: Logic Design

By archive
•
updated over 18 years ago by archive

1 replies • 13166 views
Discussion

finding latches i design

Category: Logic Design

By archive
•
updated over 18 years ago by archive

4 replies • 14944 views
Discussion

size of collection

Category: Logic Design

By archive
•
updated over 18 years ago by archive

1 replies • 18605 views
Discussion

Passing Defines during read_hdl

Category: Logic Design

By archive
•
updated over 18 years ago by archive

2 replies • 14886 views
Discussion

PLE - physical layout estimator

Category: Logic Design

By archive
•
updated over 18 years ago by archive

13 replies • 8178 views
Discussion

How to tackle Aborted properties?

Category: Logic Design

By archive
•
started over 18 years ago

0 replies • 12791 views
Discussion

How to tell conformal that some input combinations do not occur

Category: Logic Design

By archive
•
updated over 18 years ago by archive

6 replies • 16198 views
Discussion

TIP OF THE MONTH: Verifying Final Netlist

Category: Logic Design

By archive
•
started over 18 years ago

0 replies • 14355 views
Discussion

Need some more information about Trimmed index [CDFG-420]

Category: Logic Design

By archive
•
updated over 18 years ago by archive

2 replies • 13409 views
Discussion

How to handle DesignWare modules

Category: Logic Design

By archive
•
updated over 18 years ago by archive

1 replies • 14220 views
Discussion

Warning: "work.example_pkg" not found (work.example_pkg found and used)

Category: Logic Design

By archive
•
updated over 18 years ago by archive

1 replies • 5700 views
Discussion

Conformal

Category: Logic Design

By archive
•
updated over 18 years ago by archive

5 replies • 14794 views
Discussion

Incomprehensible warning when running "write hier_compare dofile"

Category: Logic Design

By archive
•
updated over 18 years ago by archive

6 replies • 7633 views
Discussion

TIP OF THE MONTH: The dangers of using "set undriven signal"

Category: Logic Design

By archive
•
started over 18 years ago

0 replies • 8331 views
Discussion

Buffer constant nets in RC

Category: Logic Design

By archive
•
updated over 18 years ago by archive

2 replies • 13824 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.