Logic Design

Latest Posts

Discussion

Best flow to map most key points before compare

Category: Logic Design

By AntonioL
•
updated over 13 years ago by AntonioL

2 replies • 14346 views
Discussion

RTL Compiler - read_tcf - Cannot read TCF file when using Generate verilog statement

Category: Logic Design

By mamsadegh
•
started over 13 years ago

0 replies • 1017 views
Discussion

RTL Compiler - "synthesize -to_generic" generated verilog netlist has delay!

Category: Logic Design

By mamsadegh
•
started over 13 years ago

0 replies • 1292 views
Discussion

RTL Compiler -- clock latency

Category: Logic Design

By amitram
•
updated over 13 years ago by grasshopper

1 replies • 1525 views
Discussion

I am using FreePDK45nm library. I couldn't synthesise a register file.

Category: Logic Design

By Thommandram
•
updated over 13 years ago by grasshopper

1 replies • 1049 views
Discussion

Procedure to define a new VHDL library in RTL compiler script

Category: Logic Design

By shustar
•
updated over 13 years ago by grasshopper

3 replies • 15072 views
Discussion

How to report leaf cell area

Category: Logic Design

By tompy
•
updated over 13 years ago by grasshopper

2 replies • 14789 views
Discussion

Ideas for integrating a full-custom designed layout with a semi-custom designed microprocessor.

Category: Logic Design

By Thommandram
•
started over 13 years ago

0 replies • 12634 views
Discussion

How to integrate a full-custom designed layout with a semi-custom designed microprocessor.

Category: Logic Design

By Thommandram
•
started over 13 years ago

0 replies • 12776 views
Discussion

CCD check fails as Encounter cannot parse a design file which has a "generate" block in it

Category: Logic Design

By dp2402
•
updated over 13 years ago by dp2402

6 replies • 5799 views
Discussion

Cadence RTL Compiler: read_tcf vs read_vcd

Category: Logic Design

By mamsadegh
•
updated over 13 years ago by grasshopper

1 replies • 14389 views
Discussion

power estimation using rc

Category: Logic Design

By RCsyn
•
started over 13 years ago

0 replies • 12850 views
Discussion

RC synthesis flows

Category: Logic Design

By sureshm
•
updated over 13 years ago by sureshm

4 replies • 16403 views
Discussion

RTL Synthesis

Category: Logic Design

By Orion007
•
started over 13 years ago

0 replies • 12736 views
Discussion

ask one question about the location of the reserve bit in register

Category: Logic Design

By redrabbit
•
updated over 13 years ago by grasshopper

1 replies • 13139 views

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