Logic Design

Latest Posts

Discussion

no constraints on hierarchial boundaries

Category: Logic Design

By tanyacool

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updated over 12 years ago by grasshopper

1 replies • 13788 views
Discussion

How do we exclued delay cells in RC

Category: Logic Design

By tanyacool

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updated over 12 years ago by grasshopper

1 replies • 13905 views
Discussion

Conformal-LP : CPF_LIB1 not flagging.

Category: Logic Design

By nitint08

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updated over 12 years ago by tstark

1 replies • 14112 views
Discussion

Conformal LP : Merging CPF files.

Category: Logic Design

By nitint08

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updated over 12 years ago by tstark

1 replies • 13902 views
Discussion

difference between Random Resistance faults and deterministic faults?

Category: Logic Design

By vipul982

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updated over 12 years ago by bmiller

1 replies • 16112 views
Discussion

How do I insert test point in the model?

Category: Logic Design

By vipul982

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started over 12 years ago

0 replies • 13668 views
Discussion

test procedure in Cadence encounter test tool?

Category: Logic Design

By vipul982

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updated over 12 years ago by vipul982

4 replies • 16508 views
Discussion

Does test compaction reduces tester time or memory or both?

Category: Logic Design

By vipul982

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updated over 12 years ago by vipul982

2 replies • 14491 views
Discussion

how to connect multi clock domians to only one scan chain

Category: Logic Design

By MoKhairy

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updated over 12 years ago by bmiller

1 replies • 15728 views
Discussion

dft settings during DFT scan insertion

Category: Logic Design

By tanyacool

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updated over 12 years ago by nannasin28

4 replies • 19358 views
Discussion

Reg .VCD file generation

Category: Logic Design

By Music

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updated over 12 years ago by nannasin28

8 replies • 22701 views
Discussion

How to handle pre defined generated clocks in .libs.

Category: Logic Design

By sureshm

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started over 12 years ago

0 replies • 15136 views
Discussion

MBIST insertion using RC tool

Category: Logic Design

By Srikanth Y

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updated over 13 years ago by Srikanth Y

2 replies • 15563 views
Discussion

Need help on forward body biasing and CSAFF&CHLFF circuit

Category: Logic Design

By ntus

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started over 13 years ago

0 replies • 690 views
Discussion

How to give a bit string as input in cadence virtuose spectre?

Category: Logic Design

By bsddsb

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started over 13 years ago

0 replies • 14137 views

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