Logic Design

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Discussion

Timing report for a hierarchical block

Category: Logic Design

By Ivan de Trble

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updated over 14 years ago by grasshopper

3 replies • 14828 views
Discussion

Help a newbie!

Category: Logic Design

By PauloRRR

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updated over 14 years ago by croy

1 replies • 13882 views
Discussion

Issue with the # clocks while synthesizing DW02_mult_4_stage component

Category: Logic Design

By sureshm

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updated over 14 years ago by grasshopper

1 replies • 13843 views
Discussion

Identifying Half Cycle paths in the design

Category: Logic Design

By sureshm

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updated over 14 years ago by grasshopper

1 replies • 16842 views
Discussion

RTL Compiler: Area "what-if" anaylsis / Area Constraints

Category: Logic Design

By maxbaker

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updated over 14 years ago by grasshopper

1 replies • 1028 views
Discussion

RTL Compiler: write_sdf and clocks

Category: Logic Design

By moogyd

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updated over 14 years ago by mclarke

3 replies • 15704 views
Discussion

RTL Compiler: Mismatch in unateness

Category: Logic Design

By Metin

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started over 14 years ago

0 replies • 13581 views
Discussion

LEC CDC Structural Checks

Category: Logic Design

By timmynolan

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updated over 14 years ago by jananee

1 replies • 14448 views
Discussion

CDC Methodology

Category: Logic Design

By sureshm

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updated over 14 years ago by Jack Ho

3 replies • 16129 views
Discussion

DONT USE cells & uncertainties

Category: Logic Design

By sureshm

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updated over 14 years ago by mclarke

2 replies • 1497 views
Discussion

RC Behavior with the effort levels

Category: Logic Design

By sureshm

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updated over 14 years ago by sandeepk

1 replies • 14025 views
Discussion

RC --- any way to dump the histogram ?

Category: Logic Design

By sureshm

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updated over 14 years ago by rokamura

2 replies • 1462 views
Discussion

description about these attributes

Category: Logic Design

By ChInNi miSSing

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started over 14 years ago

0 replies • 13904 views
Discussion

What will be the effect by using cost_groups in RC

Category: Logic Design

By ChInNi miSSing

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started over 14 years ago

0 replies • 13325 views
Discussion

Hi...is there any one working in cadence RTL compiler

Category: Logic Design

By ChInNi miSSing

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started over 14 years ago

0 replies • 13268 views

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