Logic Design

Latest Posts

Discussion

Timing report for a hierarchical block

Category: Logic Design

By Ivan de Trble
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updated over 14 years ago by grasshopper

3 replies • 13890 views
Discussion

Help a newbie!

Category: Logic Design

By PauloRRR
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updated over 14 years ago by croy

1 replies • 13059 views
Discussion

Issue with the # clocks while synthesizing DW02_mult_4_stage component

Category: Logic Design

By sureshm
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updated over 14 years ago by grasshopper

1 replies • 13087 views
Discussion

Identifying Half Cycle paths in the design

Category: Logic Design

By sureshm
•
updated over 14 years ago by grasshopper

1 replies • 15868 views
Discussion

RTL Compiler: Area "what-if" anaylsis / Area Constraints

Category: Logic Design

By maxbaker
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updated over 14 years ago by grasshopper

1 replies • 864 views
Discussion

RTL Compiler: write_sdf and clocks

Category: Logic Design

By moogyd
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updated over 14 years ago by mclarke

3 replies • 14653 views
Discussion

RTL Compiler: Mismatch in unateness

Category: Logic Design

By Metin
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started over 14 years ago

0 replies • 12837 views
Discussion

LEC CDC Structural Checks

Category: Logic Design

By timmynolan
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updated over 14 years ago by jananee

1 replies • 13542 views
Discussion

CDC Methodology

Category: Logic Design

By sureshm
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updated over 14 years ago by Jack Ho

3 replies • 14994 views
Discussion

DONT USE cells & uncertainties

Category: Logic Design

By sureshm
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updated over 14 years ago by mclarke

2 replies • 1281 views
Discussion

RC Behavior with the effort levels

Category: Logic Design

By sureshm
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updated over 14 years ago by sandeepk

1 replies • 13226 views
Discussion

RC --- any way to dump the histogram ?

Category: Logic Design

By sureshm
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updated over 14 years ago by rokamura

2 replies • 1234 views
Discussion

description about these attributes

Category: Logic Design

By ChInNi miSSing
•
started over 14 years ago

0 replies • 13157 views
Discussion

What will be the effect by using cost_groups in RC

Category: Logic Design

By ChInNi miSSing
•
started over 14 years ago

0 replies • 12651 views
Discussion

Hi...is there any one working in cadence RTL compiler

Category: Logic Design

By ChInNi miSSing
•
started over 14 years ago

0 replies • 12552 views

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