Logic Design

Latest Posts

Discussion

RTL Compiler: 1'b0/1'b1 instead of LOGIC0/LOGIC1 cells

Category: Logic Design

By archive
•
updated over 19 years ago by archive

1 replies • 1832 views
Discussion

Technology translation in RC

Category: Logic Design

By archive
•
updated over 19 years ago by archive

3 replies • 16204 views
Discussion

simplify_constants

Category: Logic Design

By archive
•
updated over 19 years ago by archive

1 replies • 15122 views
Discussion

constraining between ports and clock domain

Category: Logic Design

By archive
•
updated over 19 years ago by archive

19 replies • 27673 views
Discussion

TIP OF THE MONTH: Recommended modeling directives for RTL-gate

Category: Logic Design

By archive
•
started over 19 years ago

0 replies • 14682 views
Discussion

Choosing Hierarchy separator in RTL compiler

Category: Logic Design

By archive
•
updated over 19 years ago by archive

2 replies • 16276 views
Discussion

Clock gating cells constraints

Category: Logic Design

By archive
•
started over 19 years ago

0 replies • 15540 views
Discussion

RTL compiler: Port names expansion of record types in vhdl synthesis

Category: Logic Design

By archive
•
updated over 19 years ago by archive

2 replies • 16703 views
Discussion

How to get the latest information about Conformal?

Category: Logic Design

By archive
•
started over 19 years ago

0 replies • 14314 views
Discussion

questions on custom digital IC design

Category: Logic Design

By archive
•
started over 19 years ago

0 replies • 14643 views
Discussion

How FEV saved our STA

Category: Logic Design

By archive
•
updated over 19 years ago by archive

2 replies • 16184 views
Discussion

CDNLive! papers/presentations - excerpts/pointers for FV topics

Category: Logic Design

By archive
•
started over 20 years ago

0 replies • 1044 views
Discussion

reading synthesized design

Category: Logic Design

By archive
•
updated over 20 years ago by archive

3 replies • 16421 views
Discussion

RC compiler issue with vlog2001

Category: Logic Design

By archive
•
updated over 20 years ago by archive

1 replies • 15036 views
Discussion

Reading Netlists with SEQGEN primitive

Category: Logic Design

By archive
•
updated over 20 years ago by archive

2 replies • 17472 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.