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Logic Design

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  • Discussion

    How to handle DesignWare modules

    Category: Logic Design

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    updated over 19 years ago by archive

    1 replies • 16206 views
  • Discussion

    Warning: "work.example_pkg" not found (work.example_pkg found and used)

    Category: Logic Design

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    updated over 19 years ago by archive

    1 replies • 6043 views
  • Discussion

    Conformal

    Category: Logic Design

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    updated over 19 years ago by archive

    5 replies • 17253 views
  • Discussion

    Incomprehensible warning when running "write hier_compare dofile"

    Category: Logic Design

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    updated over 19 years ago by archive

    6 replies • 8692 views
  • Discussion

    TIP OF THE MONTH: The dangers of using "set undriven signal"

    Category: Logic Design

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    started over 19 years ago

    0 replies • 9319 views
  • Discussion

    Buffer constant nets in RC

    Category: Logic Design

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    updated over 19 years ago by archive

    2 replies • 16024 views
  • Discussion

    Versioning of files with an external CM system

    Category: Logic Design

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    updated over 19 years ago by archive

    1 replies • 14872 views
  • Discussion

    Resolving aborts after "analyze abort -compare"

    Category: Logic Design

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    updated over 19 years ago by archive

    1 replies • 3418 views
  • Discussion

    Hello ihdl users. help required - verilog to schematic conversion

    Category: Logic Design

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    updated over 19 years ago by archive

    1 replies • 1957 views
  • Discussion

    using RTL Compiler as Static Timing Analysis

    Category: Logic Design

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    updated over 19 years ago by archive

    6 replies • 19842 views
  • Discussion

    TIP OF THE MONTH: How to pack up a Conformal testcase for your Cadence AE

    Category: Logic Design

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    started over 19 years ago

    0 replies • 15133 views
  • Discussion

    Debugging RC scripts - tip

    Category: Logic Design

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    started over 19 years ago

    0 replies • 610 views
  • Discussion

    Driving not connected bus bits

    Category: Logic Design

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    updated over 19 years ago by archive

    1 replies • 15537 views
  • Discussion

    Clock networks in RC

    Category: Logic Design

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    updated over 19 years ago by archive

    1 replies • 15120 views
  • Discussion

    ideal network in RC

    Category: Logic Design

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    updated over 19 years ago by archive

    1 replies • 16609 views
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