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Logic Design

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  • Discussion

    Conformal

    Category: Logic Design

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    updated over 19 years ago by archive

    5 replies • 17111 views
  • Discussion

    Incomprehensible warning when running "write hier_compare dofile"

    Category: Logic Design

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    updated over 19 years ago by archive

    6 replies • 8564 views
  • Discussion

    TIP OF THE MONTH: The dangers of using "set undriven signal"

    Category: Logic Design

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    started over 19 years ago

    0 replies • 9212 views
  • Discussion

    Buffer constant nets in RC

    Category: Logic Design

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    updated over 19 years ago by archive

    2 replies • 15916 views
  • Discussion

    Versioning of files with an external CM system

    Category: Logic Design

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    updated over 19 years ago by archive

    1 replies • 14825 views
  • Discussion

    Resolving aborts after "analyze abort -compare"

    Category: Logic Design

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    updated over 19 years ago by archive

    1 replies • 3315 views
  • Discussion

    Hello ihdl users. help required - verilog to schematic conversion

    Category: Logic Design

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    updated over 19 years ago by archive

    1 replies • 1899 views
  • Discussion

    using RTL Compiler as Static Timing Analysis

    Category: Logic Design

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    updated over 19 years ago by archive

    6 replies • 19635 views
  • Discussion

    TIP OF THE MONTH: How to pack up a Conformal testcase for your Cadence AE

    Category: Logic Design

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    started over 19 years ago

    0 replies • 15073 views
  • Discussion

    Debugging RC scripts - tip

    Category: Logic Design

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    started over 19 years ago

    0 replies • 568 views
  • Discussion

    Driving not connected bus bits

    Category: Logic Design

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    updated over 19 years ago by archive

    1 replies • 15349 views
  • Discussion

    Clock networks in RC

    Category: Logic Design

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    updated over 19 years ago by archive

    1 replies • 15038 views
  • Discussion

    ideal network in RC

    Category: Logic Design

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    updated over 19 years ago by archive

    1 replies • 16547 views
  • Discussion

    RTL Compiler: 1'b0/1'b1 instead of LOGIC0/LOGIC1 cells

    Category: Logic Design

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    updated over 19 years ago by archive

    1 replies • 1761 views
  • Discussion

    Technology translation in RC

    Category: Logic Design

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    updated over 19 years ago by archive

    3 replies • 16119 views
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